376 lines
9 KiB
ArmAsm
376 lines
9 KiB
ArmAsm
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Linus Nielsen Feltzing
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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.section .init.text,"ax",%progbits
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.global start
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start:
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/* PortalPlayer bootloader and startup code based on startup.s from the iPodLinux
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* loader
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*
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* Copyright (c) 2003, Daniel Palffy (dpalffy (at) rainstorm.org)
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* Copyright (c) 2005, Bernard Leach <leachbj@bouncycastle.org>
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*
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*/
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#if CONFIG_CPU == PP5002
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.equ PROC_ID, 0xc4000000
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.equ COP_CTRL, 0xcf004058
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.equ COP_STATUS, 0xcf004050
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.equ IIS_CONFIG, 0xc0002500
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.equ SLEEP, 0xca
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.equ WAKE, 0xce
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.equ SLEEPING, 0x4000
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#else
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.equ PROC_ID, 0x60000000
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.equ COP_CTRL, 0x60007004
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.equ COP_STATUS, 0x60007004
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.equ IIS_CONFIG, 0x70002800
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.equ SLEEP, 0x80000000
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.equ WAKE, 0x0
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.equ SLEEPING, 0x80000000
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#endif
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msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ */
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#ifndef BOOTLOADER
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b pad_skip
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.space 50*4 /* (more than enough) space for exception vectors */
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pad_skip:
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/* We need to remap memory from wherever SDRAM is mapped natively, to
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base address 0, so we can put our exception vectors there. We don't
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want to do this remapping while executing from SDRAM, so we copy the
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remapping code to IRAM, then execute from there. Hence, the following
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code is compiled for address 0, but is currently executing at either
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0x28000000 or 0x10000000, depending on chipset version. Do not use any
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absolute addresses until remapping has been done. */
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ldr r1, =0x40000000
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ldr r2, =remap_start
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ldr r3, =remap_end
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and r5, pc, #0xff000000 /* adjust for execute address */
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orr r2, r2, r5
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orr r3, r3, r5
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/* copy the code to 0x40000000 */
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1:
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ldr r4, [r2], #4
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str r4, [r1], #4
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cmp r2, r3
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ble 1b
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ldr r3, =0x3f84 /* r3 and r1 values here are magic, don't touch */
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orr r3, r3, r5 /* adjust for execute address */
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ldr r2, =0xf000f014
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mov r1, #0x3a00
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ldr r0, =0xf000f010
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mov pc, #0x40000000
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remap_start:
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str r1, [r0]
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str r3, [r2]
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ldr r0, L_post_remap
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mov pc, r0
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L_post_remap: .word remap_end
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remap_end:
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/* After doing the remapping, send the COP to sleep.
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On wakeup it will go to cop_init */
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ldr r0, =PROC_ID
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ldr r0, [r0]
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and r0, r0, #0xff
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cmp r0, #0x55
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beq 1f
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/* put us (co-processor) to sleep */
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ldr r4, =COP_CTRL
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mov r3, #SLEEP
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str r3, [r4]
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ldr pc, =cop_init
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1:
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#ifndef DEBUG
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/* Copy exception handler code to address 0 */
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ldr r2, =_vectorsstart
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ldr r3, =_vectorsend
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ldr r4, =_vectorscopy
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1:
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cmp r3, r2
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ldrhi r5, [r4], #4
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strhi r5, [r2], #4
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bhi 1b
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#else
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ldr r1, =vectors
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ldr r0, =irq_handler
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str r0, [r1, #24]
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ldr r0, =fiq_handler
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str r0, [r1, #28]
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#endif
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#ifndef STUB
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/* Zero out IBSS */
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ldr r2, =_iedata
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ldr r3, =_iend
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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/* Copy the IRAM */
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ldr r2, =_iramcopy
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ldr r3, =_iramstart
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ldr r4, =_iramend
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1:
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cmp r4, r3
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ldrhi r5, [r2], #4
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strhi r5, [r3], #4
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bhi 1b
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#endif /* !STUB */
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#endif /* !BOOTLOADER */
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/* Initialise bss section to zero */
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ldr r2, =_edata
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ldr r3, =_end
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mov r4, #0
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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/* Set up some stack and munge it with 0xdeadbeef */
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ldr sp, =stackend
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mov r3, sp
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ldr r2, =stackbegin
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ldr r4, =0xdeadbeef
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1:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 1b
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#ifdef BOOTLOADER
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/* TODO: the high part of the address is probably dependent on CONFIG_CPU.
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Since we tend to use ifdefs for each chipset target
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anyway, we might as well just hardcode it here.
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*/
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/* get the high part of our execute address */
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ldr r0, =0xff000000
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and r8, pc, r0 @ r8 is used later
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/* Find out which processor we are */
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mov r0, #PROC_ID
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ldr r0, [r0]
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and r0, r0, #0xff
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cmp r0, #0x55
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beq 1f
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/* put us (co-processor) to sleep */
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ldr r4, =COP_CTRL
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mov r3, #SLEEP
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str r3, [r4]
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ldr pc, =cop_wake_start
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cop_wake_start:
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/* jump the COP to startup */
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ldr r0, =startup_loc
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ldr pc, [r0]
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1:
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/* get the high part of our execute address */
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ldr r2, =0xffffff00
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and r4, pc, r2
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/* Copy bootloader to safe area - 0x40000000 */
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mov r5, #0x40000000
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ldr r6, = _dataend
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sub r0, r6, r5 /* length of loader */
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add r0, r4, r0 /* r0 points to start of loader */
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1:
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cmp r5, r6
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ldrcc r2, [r4], #4
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strcc r2, [r5], #4
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bcc 1b
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ldr pc, =start_loc /* jump to the relocated start_loc: */
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start_loc:
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/* execute the loader - this will load an image to 0x10000000 */
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bl main
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/* Wake up the coprocessor before executing the firmware */
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/* save the startup address for the COP */
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ldr r1, =startup_loc
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str r0, [r1]
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/* make sure COP is sleeping */
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ldr r4, =COP_STATUS
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1:
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ldr r3, [r4]
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ands r3, r3, #SLEEPING
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beq 1b
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/* wake up COP */
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ldr r4, =COP_CTRL
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mov r3, #WAKE
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str r3, [r4]
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/* jump to start location */
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mov pc, r0
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startup_loc:
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.word 0x0
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.align 8 /* starts at 0x100 */
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.global boot_table
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boot_table:
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/* here comes the boot table, don't move its offset */
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.space 400
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#else /* BOOTLOADER */
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/* Set up stack for IRQ mode */
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msr cpsr_c, #0xd2
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ldr sp, =irq_stack
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/* Set up stack for FIQ mode */
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msr cpsr_c, #0xd1
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ldr sp, =fiq_stack
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/* We'll load the banked FIQ mode registers with useful values here.
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These values will be used in the FIQ handler in pcm_playback.c */
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ldr r12, =IIS_CONFIG
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ldr r11, =p
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/* Let abort and undefined modes use IRQ stack */
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msr cpsr_c, #0xd7
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ldr sp, =irq_stack
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msr cpsr_c, #0xdb
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ldr sp, =irq_stack
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/* Switch to supervisor mode */
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msr cpsr_c, #0xd3
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ldr sp, =stackend
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bl main
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/* main() should never return */
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cop_init:
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ldr sp, =cop_stackend
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mov r3, sp
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ldr r2, =cop_stackbegin
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ldr r4, =0xdeadbeef
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2:
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cmp r3, r2
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strhi r4, [r2], #4
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bhi 2b
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ldr sp, =cop_stackend
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bl cop_main
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/* Exception handlers. Will be copied to address 0 after memory remapping */
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.section .vectors,"aw"
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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ldr pc, [pc, #24]
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/* Exception vectors */
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.global vectors
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vectors:
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.word start
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.word undef_instr_handler
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.word software_int_handler
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.word prefetch_abort_handler
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.word data_abort_handler
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.word reserved_handler
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.word irq_handler
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.word fiq_handler
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.text
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#ifndef STUB
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.global irq
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.global fiq
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.global UIE
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#endif
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/* All illegal exceptions call into UIE with exception address as first
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parameter. This is calculated differently depending on which exception
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we're in. Second parameter is exception number, used for a string lookup
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in UIE.
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*/
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undef_instr_handler:
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mov r0, lr
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mov r1, #0
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b UIE
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/* We run supervisor mode most of the time, and should never see a software
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exception being thrown. Perhaps make it illegal and call UIE?
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*/
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software_int_handler:
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reserved_handler:
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movs pc, lr
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prefetch_abort_handler:
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sub r0, lr, #4
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mov r1, #1
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b UIE
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fiq_handler:
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@ Branch straight to FIQ handler in pcm_playback.c. This also handles the
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@ the correct return sequence.
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ldr pc, =fiq
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data_abort_handler:
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sub r0, lr, #8
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mov r1, #2
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b UIE
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irq_handler:
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#ifndef STUB
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stmfd sp!, {r0-r3, r12, lr}
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bl irq
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ldmfd sp!, {r0-r3, r12, lr}
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#endif
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subs pc, lr, #4
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#ifdef STUB
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UIE:
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b UIE
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#endif
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/* 256 words of IRQ stack */
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.space 256*4
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irq_stack:
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/* 256 words of FIQ stack */
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.space 256*4
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fiq_stack:
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#endif /* BOOTLOADER */
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