2007-04-22 12:03:17 +00:00
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Alan Korr
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#ifndef BOOTLOADER
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extern void TIMER1(void);
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extern void TIMER2(void);
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2007-07-29 08:03:21 +00:00
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extern void ipod_3g_button_int(void);
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2007-07-30 23:48:03 +00:00
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extern void ipod_2g_adc_int(void);
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2007-04-22 12:03:17 +00:00
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void irq(void)
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{
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if(CURRENT_CORE == CPU)
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{
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if (CPU_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (CPU_INT_STAT & TIMER2_MASK)
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TIMER2();
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2007-07-29 08:03:21 +00:00
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else if (CPU_INT_STAT & GPIO_MASK)
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2007-07-30 23:48:03 +00:00
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{
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if (GPIOA_INT_STAT)
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ipod_3g_button_int();
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#ifdef IPOD_1G2G
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if (GPIOB_INT_STAT & 0x04)
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ipod_2g_adc_int();
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#endif
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}
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}
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else
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{
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2007-04-22 12:03:17 +00:00
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if (COP_INT_STAT & TIMER1_MASK)
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TIMER1();
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else if (COP_INT_STAT & TIMER2_MASK)
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TIMER2();
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}
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}
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#endif
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unsigned int current_core(void)
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{
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if(((*(volatile unsigned long *)(0xc4000000)) & 0xff) == 0x55)
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{
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return CPU;
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}
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return COP;
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}
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/* TODO: The following two function have been lifted straight from IPL, and
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hence have a lot of numeric addresses used straight. I'd like to use
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#defines for these, but don't know what most of them are for or even what
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they should be named. Because of this I also have no way of knowing how
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to extend the funtions to do alternate cache configurations and/or
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some other CPU frequency scaling. */
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#ifndef BOOTLOADER
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static void ipod_init_cache(void)
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{
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int i =0;
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/* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
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outl(inl(0xcf004050) & ~0x700, 0xcf004050);
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outl(0x4000, 0xcf004020);
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outl(0x2, 0xcf004024);
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/* PP5002 has 8KB cache */
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for (i = 0xf0004000; i < (int)(0xf0006000); i += 16) {
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outl(0x0, i);
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}
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outl(0x0, 0xf000f020);
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outl(0x3fc0, 0xf000f024);
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outl(0x3, 0xcf004024);
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}
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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2007-07-31 10:56:50 +00:00
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#else
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static void pp_set_cpu_frequency(long frequency)
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#endif
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2007-04-22 12:03:17 +00:00
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{
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2007-07-31 10:56:50 +00:00
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cpu_frequency = frequency;
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2007-04-22 12:03:17 +00:00
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2007-07-31 10:56:50 +00:00
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PLL_CONTROL |= 0x6000; /* make sure some enable bits are set */
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CLOCK_ENABLE = 0x01; /* select source #1 */
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2007-04-22 12:03:17 +00:00
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2007-07-31 10:56:50 +00:00
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switch (frequency)
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{
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case CPUFREQ_MAX:
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PLL_UNLOCK = 0xd19b; /* unlock frequencies > 66MHz */
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CLOCK_SOURCE = 0xa9; /* source #1: 24 Mhz, source #2..#4: PLL */
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PLL_CONTROL = 0xe000; /* PLL enabled */
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PLL_DIV = 3; /* 10/3 * 24MHz */
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PLL_MULT = 10;
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udelay(200); /* wait for relock */
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break;
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case CPUFREQ_NORMAL:
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CLOCK_SOURCE = 0xa9; /* source #1: 24 Mhz, source #2..#4: PLL */
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PLL_CONTROL = 0xe000; /* PLL enabled */
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PLL_DIV = 4; /* 5/4 * 24MHz */
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PLL_MULT = 5;
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udelay(200); /* wait for relock */
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break;
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case CPUFREQ_SLEEP:
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CLOCK_SOURCE = 0x51; /* source #2: 32kHz, #1, #2, #4: 24MHz */
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PLL_CONTROL = 0x6000; /* PLL disabled */
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udelay(10000); /* let 32kHz source stabilize? */
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break;
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default:
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CLOCK_SOURCE = 0x55; /* source #1..#4: 24 Mhz */
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PLL_CONTROL = 0x6000; /* PLL disabled */
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cpu_frequency = CPUFREQ_DEFAULT;
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break;
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2007-04-22 12:03:17 +00:00
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}
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2007-07-31 10:56:50 +00:00
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CLOCK_ENABLE = 0x02; /* select source #2 */
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2007-04-22 12:03:17 +00:00
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}
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2007-07-31 10:56:50 +00:00
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#endif /* !BOOTLOADER */
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2007-04-22 12:03:17 +00:00
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void system_init(void)
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{
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#ifndef BOOTLOADER
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if (CURRENT_CORE == CPU)
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{
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/* Remap the flash ROM from 0x00000000 to 0x20000000. */
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MMAP3_LOGICAL = 0x20000000 | 0x3a00;
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MMAP3_PHYSICAL = 0x00000000 | 0x3f84;
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2007-07-29 07:50:34 +00:00
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INT_FORCED_CLR = -1;
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CPU_INT_CLR = -1;
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COP_INT_CLR = -1;
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GPIOA_INT_EN = 0;
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GPIOB_INT_EN = 0;
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GPIOC_INT_EN = 0;
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GPIOD_INT_EN = 0;
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2007-04-22 12:03:17 +00:00
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#ifndef HAVE_ADJUSTABLE_CPU_FREQ
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2007-07-31 10:56:50 +00:00
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pp_set_cpu_frequency(CPUFREQ_MAX);
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2007-04-22 12:03:17 +00:00
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#endif
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}
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ipod_init_cache();
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#endif
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}
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void system_reboot(void)
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{
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2007-07-31 10:56:50 +00:00
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DEV_RS |= 4;
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2007-04-22 12:03:17 +00:00
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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