2002-04-21 22:06:12 +00:00
|
|
|
/***************************************************************************
|
|
|
|
* __________ __ ___.
|
|
|
|
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
|
|
|
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
|
|
|
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
|
|
|
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
|
|
|
* \/ \/ \/ \/ \/
|
|
|
|
* $Id$
|
|
|
|
*
|
|
|
|
* Copyright (C) 2002 by Alan Korr
|
|
|
|
*
|
|
|
|
* All files in this archive are subject to the GNU General Public License.
|
|
|
|
* See the file COPYING in the source tree root for full license agreement.
|
|
|
|
*
|
|
|
|
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
|
|
|
* KIND, either express or implied.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
2002-05-13 19:22:38 +00:00
|
|
|
#include <stdbool.h>
|
2002-04-21 22:06:12 +00:00
|
|
|
#include "ata.h"
|
|
|
|
#include "kernel.h"
|
2002-07-16 14:07:47 +00:00
|
|
|
#include "thread.h"
|
2002-04-21 22:06:12 +00:00
|
|
|
#include "led.h"
|
2002-04-27 20:14:01 +00:00
|
|
|
#include "sh7034.h"
|
|
|
|
#include "system.h"
|
2002-05-07 22:59:03 +00:00
|
|
|
#include "debug.h"
|
2002-06-18 12:53:02 +00:00
|
|
|
#include "panic.h"
|
2002-07-16 14:07:47 +00:00
|
|
|
#include "usb.h"
|
2002-08-01 12:00:03 +00:00
|
|
|
#include "power.h"
|
2002-08-15 12:54:52 +00:00
|
|
|
#include "string.h"
|
2003-09-01 05:48:42 +00:00
|
|
|
#include "hwcompat.h"
|
2002-04-21 22:06:12 +00:00
|
|
|
|
2004-07-05 13:44:53 +00:00
|
|
|
/* Uncomment the matching #define to use plain C code instead if the tweaked
|
|
|
|
* assembler code for disk reading or writing should cause problems. */
|
|
|
|
/* #define PREFER_C_READING */
|
|
|
|
/* #define PREFER_C_WRITING */
|
2004-02-15 08:44:02 +00:00
|
|
|
|
2002-06-12 09:28:22 +00:00
|
|
|
#define SECTOR_SIZE 512
|
2002-04-21 22:06:12 +00:00
|
|
|
#define ATA_DATA (*((volatile unsigned short*)0x06104100))
|
|
|
|
#define ATA_ERROR (*((volatile unsigned char*)0x06100101))
|
|
|
|
#define ATA_FEATURE ATA_ERROR
|
|
|
|
#define ATA_NSECTOR (*((volatile unsigned char*)0x06100102))
|
|
|
|
#define ATA_SECTOR (*((volatile unsigned char*)0x06100103))
|
|
|
|
#define ATA_LCYL (*((volatile unsigned char*)0x06100104))
|
|
|
|
#define ATA_HCYL (*((volatile unsigned char*)0x06100105))
|
|
|
|
#define ATA_SELECT (*((volatile unsigned char*)0x06100106))
|
|
|
|
#define ATA_COMMAND (*((volatile unsigned char*)0x06100107))
|
2002-05-08 08:27:44 +00:00
|
|
|
#define ATA_STATUS (*((volatile unsigned char*)0x06100107))
|
2002-06-12 13:51:31 +00:00
|
|
|
|
|
|
|
#define ATA_CONTROL1 ((volatile unsigned char*)0x06200206)
|
|
|
|
#define ATA_CONTROL2 ((volatile unsigned char*)0x06200306)
|
|
|
|
|
|
|
|
#define ATA_CONTROL (*ata_control)
|
2002-04-27 14:19:00 +00:00
|
|
|
#define ATA_ALT_STATUS ATA_CONTROL
|
2002-04-21 22:06:12 +00:00
|
|
|
|
2002-05-22 14:37:36 +00:00
|
|
|
#define SELECT_DEVICE1 0x10
|
2002-04-21 22:06:12 +00:00
|
|
|
#define SELECT_LBA 0x40
|
|
|
|
|
|
|
|
#define STATUS_BSY 0x80
|
|
|
|
#define STATUS_RDY 0x40
|
2002-09-24 17:10:03 +00:00
|
|
|
#define STATUS_DF 0x20
|
2002-04-21 22:06:12 +00:00
|
|
|
#define STATUS_DRQ 0x08
|
|
|
|
#define STATUS_ERR 0x01
|
|
|
|
|
2004-03-02 09:55:23 +00:00
|
|
|
#define ERROR_ABRT 0x04
|
|
|
|
|
2002-04-21 22:06:12 +00:00
|
|
|
#define CONTROL_nIEN 0x02
|
|
|
|
#define CONTROL_SRST 0x04
|
|
|
|
|
|
|
|
#define CMD_READ_SECTORS 0x20
|
|
|
|
#define CMD_WRITE_SECTORS 0x30
|
2002-09-05 15:25:08 +00:00
|
|
|
#define CMD_READ_MULTIPLE 0xC4
|
|
|
|
#define CMD_WRITE_MULTIPLE 0xC5
|
|
|
|
#define CMD_SET_MULTIPLE_MODE 0xC6
|
2002-04-21 22:06:12 +00:00
|
|
|
#define CMD_STANDBY_IMMEDIATE 0xE0
|
|
|
|
#define CMD_STANDBY 0xE2
|
2002-09-05 15:25:08 +00:00
|
|
|
#define CMD_IDENTIFY 0xEC
|
2002-04-21 22:06:12 +00:00
|
|
|
#define CMD_SLEEP 0xE6
|
2004-01-14 13:15:19 +00:00
|
|
|
#define CMD_SET_FEATURES 0xEF
|
2002-04-21 22:06:12 +00:00
|
|
|
#define CMD_SECURITY_FREEZE_LOCK 0xF5
|
|
|
|
|
2002-07-16 14:07:47 +00:00
|
|
|
#define Q_SLEEP 0
|
|
|
|
|
2002-09-24 14:23:18 +00:00
|
|
|
#define READ_TIMEOUT 5*HZ
|
|
|
|
|
2002-05-22 14:37:36 +00:00
|
|
|
static struct mutex ata_mtx;
|
2002-07-02 14:23:30 +00:00
|
|
|
char ata_device; /* device 0 (master) or 1 (slave) */
|
|
|
|
int ata_io_address; /* 0x300 or 0x200, only valid on recorder */
|
2002-06-12 13:51:31 +00:00
|
|
|
static volatile unsigned char* ata_control;
|
|
|
|
|
2002-06-26 12:36:29 +00:00
|
|
|
bool old_recorder = false;
|
2002-12-04 14:58:48 +00:00
|
|
|
int ata_spinup_time = 0;
|
2002-12-06 15:17:30 +00:00
|
|
|
static bool spinup = false;
|
2003-07-18 21:55:06 +00:00
|
|
|
static bool sleeping = true;
|
2002-07-16 14:07:47 +00:00
|
|
|
static int sleep_timeout = 5*HZ;
|
2002-11-27 15:55:47 +00:00
|
|
|
static bool poweroff = false;
|
2002-11-29 07:05:27 +00:00
|
|
|
#ifdef HAVE_ATA_POWER_OFF
|
2002-11-27 15:55:47 +00:00
|
|
|
static int poweroff_timeout = 2*HZ;
|
|
|
|
#endif
|
2002-07-16 14:07:47 +00:00
|
|
|
static char ata_stack[DEFAULT_STACK_SIZE];
|
|
|
|
static char ata_thread_name[] = "ata";
|
|
|
|
static struct event_queue ata_queue;
|
|
|
|
static bool initialized = false;
|
2002-08-15 12:42:37 +00:00
|
|
|
static bool delayed_write = false;
|
|
|
|
static unsigned char delayed_sector[SECTOR_SIZE];
|
|
|
|
static int delayed_sector_num;
|
2002-06-26 12:36:29 +00:00
|
|
|
|
2002-08-26 13:21:14 +00:00
|
|
|
static long last_user_activity = -1;
|
2002-09-23 11:39:21 +00:00
|
|
|
long last_disk_activity = -1;
|
2002-08-26 13:21:14 +00:00
|
|
|
|
2002-09-05 15:25:08 +00:00
|
|
|
static int multisectors; /* number of supported multisectors */
|
|
|
|
static unsigned short identify_info[SECTOR_SIZE];
|
|
|
|
|
2002-08-02 06:01:22 +00:00
|
|
|
static int ata_power_on(void);
|
2002-08-27 21:06:48 +00:00
|
|
|
static int perform_soft_reset(void);
|
2002-12-02 10:30:40 +00:00
|
|
|
static int set_multiple_mode(int sectors);
|
2004-02-17 01:31:50 +00:00
|
|
|
static int set_features(void);
|
2002-08-27 21:06:48 +00:00
|
|
|
|
2002-08-01 08:15:58 +00:00
|
|
|
static int wait_for_bsy(void) __attribute__ ((section (".icode")));
|
2002-04-21 22:06:12 +00:00
|
|
|
static int wait_for_bsy(void)
|
|
|
|
{
|
2004-03-19 13:26:43 +00:00
|
|
|
int timeout = current_tick + HZ*30;
|
2003-07-10 13:32:15 +00:00
|
|
|
while (TIME_BEFORE(current_tick, timeout) && (ATA_STATUS & STATUS_BSY)) {
|
|
|
|
last_disk_activity = current_tick;
|
2003-04-11 07:43:04 +00:00
|
|
|
yield();
|
2003-07-10 13:32:15 +00:00
|
|
|
}
|
2002-04-21 22:06:12 +00:00
|
|
|
|
|
|
|
if (TIME_BEFORE(current_tick, timeout))
|
|
|
|
return 1;
|
|
|
|
else
|
|
|
|
return 0; /* timeout */
|
|
|
|
}
|
|
|
|
|
2002-08-01 08:15:58 +00:00
|
|
|
static int wait_for_rdy(void) __attribute__ ((section (".icode")));
|
2002-04-21 22:06:12 +00:00
|
|
|
static int wait_for_rdy(void)
|
|
|
|
{
|
2002-08-29 11:50:57 +00:00
|
|
|
int timeout;
|
|
|
|
|
2002-04-21 22:06:12 +00:00
|
|
|
if (!wait_for_bsy())
|
|
|
|
return 0;
|
2002-08-29 11:50:57 +00:00
|
|
|
|
2002-09-04 20:15:45 +00:00
|
|
|
timeout = current_tick + HZ*10;
|
2003-03-31 14:14:07 +00:00
|
|
|
|
2003-07-10 13:32:15 +00:00
|
|
|
while (TIME_BEFORE(current_tick, timeout) &&
|
|
|
|
!(ATA_ALT_STATUS & STATUS_RDY)) {
|
|
|
|
last_disk_activity = current_tick;
|
2003-04-11 07:43:04 +00:00
|
|
|
yield();
|
2003-07-10 13:32:15 +00:00
|
|
|
}
|
2002-08-29 11:50:57 +00:00
|
|
|
|
|
|
|
if (TIME_BEFORE(current_tick, timeout))
|
|
|
|
return STATUS_RDY;
|
|
|
|
else
|
|
|
|
return 0; /* timeout */
|
2002-04-21 22:06:12 +00:00
|
|
|
}
|
|
|
|
|
2002-08-01 08:15:58 +00:00
|
|
|
static int wait_for_start_of_transfer(void) __attribute__ ((section (".icode")));
|
2002-04-21 22:06:12 +00:00
|
|
|
static int wait_for_start_of_transfer(void)
|
|
|
|
{
|
|
|
|
if (!wait_for_bsy())
|
|
|
|
return 0;
|
2002-04-27 14:19:00 +00:00
|
|
|
return (ATA_ALT_STATUS & (STATUS_BSY|STATUS_DRQ)) == STATUS_DRQ;
|
|
|
|
}
|
2002-04-21 22:06:12 +00:00
|
|
|
|
2002-08-01 08:15:58 +00:00
|
|
|
static int wait_for_end_of_transfer(void) __attribute__ ((section (".icode")));
|
2002-04-21 22:06:12 +00:00
|
|
|
static int wait_for_end_of_transfer(void)
|
|
|
|
{
|
|
|
|
if (!wait_for_bsy())
|
|
|
|
return 0;
|
2002-04-27 14:19:00 +00:00
|
|
|
return (ATA_ALT_STATUS & (STATUS_RDY|STATUS_DRQ)) == STATUS_RDY;
|
2002-04-21 22:06:12 +00:00
|
|
|
}
|
|
|
|
|
2004-01-16 09:02:21 +00:00
|
|
|
|
|
|
|
/* the tight loop of ata_read_sectors(), to avoid the whole in IRAM */
|
|
|
|
static void copy_read_sectors(unsigned char* buf,
|
|
|
|
int wordcount)
|
|
|
|
__attribute__ ((section (".icode")));
|
|
|
|
static void copy_read_sectors(unsigned char* buf, int wordcount)
|
|
|
|
{
|
2004-07-05 13:44:53 +00:00
|
|
|
#ifdef PREFER_C_READING
|
2004-03-10 14:15:14 +00:00
|
|
|
unsigned short tmp = 0;
|
2004-01-16 09:02:21 +00:00
|
|
|
|
2004-03-10 14:15:14 +00:00
|
|
|
if ( (unsigned int)buf & 1)
|
2004-01-27 09:12:51 +00:00
|
|
|
{ /* not 16-bit aligned, copy byte by byte */
|
2004-01-16 09:02:21 +00:00
|
|
|
unsigned char* bufend = buf + wordcount*2;
|
|
|
|
do
|
2004-01-27 09:12:51 +00:00
|
|
|
{ /* loop compiles to 9 assembler instructions */
|
2004-06-11 06:56:51 +00:00
|
|
|
/* takes 14 clock cycles (2 pipeline stalls, 1 wait) */
|
2004-01-27 09:12:51 +00:00
|
|
|
tmp = ATA_DATA;
|
2004-01-16 09:02:21 +00:00
|
|
|
*buf++ = tmp & 0xff; /* I assume big endian */
|
|
|
|
*buf++ = tmp >> 8; /* and don't use the SWAB16 macro */
|
|
|
|
} while (buf < bufend); /* tail loop is faster */
|
|
|
|
}
|
2004-03-10 14:15:14 +00:00
|
|
|
else
|
2004-01-27 09:12:51 +00:00
|
|
|
{ /* 16-bit aligned, can do faster copy */
|
2004-01-16 09:02:21 +00:00
|
|
|
unsigned short* wbuf = (unsigned short*)buf;
|
|
|
|
unsigned short* wbufend = wbuf + wordcount;
|
|
|
|
do
|
|
|
|
{ /* loop compiles to 7 assembler instructions */
|
2004-06-11 06:56:51 +00:00
|
|
|
/* takes 12 clock cycles (2 pipeline stalls, 1 wait) */
|
2004-01-16 09:02:21 +00:00
|
|
|
*wbuf = SWAB16(ATA_DATA);
|
|
|
|
} while (++wbuf < wbufend); /* tail loop is faster */
|
2004-03-10 14:15:14 +00:00
|
|
|
}
|
2004-01-27 09:12:51 +00:00
|
|
|
#else
|
2004-03-10 14:15:14 +00:00
|
|
|
/* turbo-charged assembler version */
|
|
|
|
/* this assumes wordcount to be a multiple of 4 */
|
|
|
|
asm (
|
|
|
|
"add %1,%1 \n" /* wordcount -> bytecount */
|
|
|
|
"add %0,%1 \n" /* bytecount -> bufend */
|
|
|
|
"mov %0,r0 \n"
|
|
|
|
"tst #1,r0 \n" /* 16-bit aligned ? */
|
|
|
|
"bt .aligned \n" /* yes, do word copy */
|
|
|
|
|
|
|
|
/* not 16-bit aligned */
|
|
|
|
"mov #-1,r3 \n" /* prepare a bit mask for high byte */
|
2004-04-01 05:46:31 +00:00
|
|
|
"shll8 r3 \n" /* r3 = 0xFFFFFF00 */
|
2004-03-10 14:15:14 +00:00
|
|
|
|
|
|
|
"mov.w @%2,r2 \n" /* read first word (1st round) */
|
|
|
|
"add #-12,%1 \n" /* adjust end address for offsets */
|
|
|
|
"mov.b r2,@%0 \n" /* store low byte of first word */
|
|
|
|
"bra .start4_b \n" /* jump into loop after next instr. */
|
|
|
|
"add #-5,%0 \n" /* adjust for dest. offsets; now even */
|
|
|
|
|
2004-04-01 05:46:31 +00:00
|
|
|
".align 2 \n"
|
2004-03-10 14:15:14 +00:00
|
|
|
".loop4_b: \n" /* main loop: copy 4 words in a row */
|
|
|
|
"mov.w @%2,r2 \n" /* read first word (2+ round) */
|
|
|
|
"and r3,r1 \n" /* get high byte of fourth word (2+ round) */
|
|
|
|
"extu.b r2,r0 \n" /* get low byte of first word (2+ round) */
|
|
|
|
"or r1,r0 \n" /* combine with high byte of fourth word */
|
|
|
|
"mov.w r0,@(4,%0) \n" /* store at buf[4] */
|
|
|
|
"nop \n" /* maintain alignment */
|
|
|
|
".start4_b: \n"
|
|
|
|
"mov.w @%2,r1 \n" /* read second word */
|
|
|
|
"and r3,r2 \n" /* get high byte of first word */
|
|
|
|
"extu.b r1,r0 \n" /* get low byte of second word */
|
|
|
|
"or r2,r0 \n" /* combine with high byte of first word */
|
|
|
|
"mov.w r0,@(6,%0) \n" /* store at buf[6] */
|
|
|
|
"add #8,%0 \n" /* buf += 8 */
|
|
|
|
"mov.w @%2,r2 \n" /* read third word */
|
|
|
|
"and r3,r1 \n" /* get high byte of second word */
|
|
|
|
"extu.b r2,r0 \n" /* get low byte of third word */
|
|
|
|
"or r1,r0 \n" /* combine with high byte of second word */
|
|
|
|
"mov.w r0,@%0 \n" /* store at buf[0] */
|
|
|
|
"cmp/hi %0,%1 \n" /* check for end */
|
|
|
|
"mov.w @%2,r1 \n" /* read fourth word */
|
|
|
|
"and r3,r2 \n" /* get high byte of third word */
|
|
|
|
"extu.b r1,r0 \n" /* get low byte of fourth word */
|
|
|
|
"or r2,r0 \n" /* combine with high byte of third word */
|
|
|
|
"mov.w r0,@(2,%0) \n" /* store at buf[2] */
|
|
|
|
"bt .loop4_b \n"
|
2004-06-11 06:56:51 +00:00
|
|
|
/* 24 instructions for 4 copies, takes 30 clock cycles (4 wait) */
|
|
|
|
/* avg. 7.5 cycles per word - 86% faster */
|
2004-03-10 14:15:14 +00:00
|
|
|
|
|
|
|
"swap.b r1,r0 \n" /* get high byte of last word */
|
|
|
|
"bra .exit \n"
|
2004-04-01 05:46:31 +00:00
|
|
|
"mov.b r0,@(4,%0) \n" /* and store it */
|
2004-03-10 14:15:14 +00:00
|
|
|
|
|
|
|
".align 2 \n"
|
|
|
|
/* 16-bit aligned, loop(read and store word) */
|
|
|
|
".aligned: \n"
|
|
|
|
"mov.w @%2,r2 \n" /* read first word (1st round) */
|
|
|
|
"add #-12,%1 \n" /* adjust end address for offsets */
|
|
|
|
"bra .start4_w \n" /* jump into loop after next instr. */
|
|
|
|
"add #-6,%0 \n" /* adjust for destination offsets */
|
|
|
|
|
|
|
|
".loop4_w: \n" /* main loop: copy 4 words in a row */
|
|
|
|
"mov.w @%2,r2 \n" /* read first word (2+ round) */
|
|
|
|
"swap.b r1,r0 \n" /* swap fourth word (2+ round) */
|
|
|
|
"mov.w r0,@(4,%0) \n" /* store fourth word (2+ round) */
|
|
|
|
"nop \n" /* maintain alignment */
|
|
|
|
".start4_w: \n"
|
|
|
|
"mov.w @%2,r1 \n" /* read second word */
|
|
|
|
"swap.b r2,r0 \n" /* swap first word */
|
|
|
|
"mov.w r0,@(6,%0) \n" /* store first word in buf[6] */
|
|
|
|
"add #8,%0 \n" /* buf += 8 */
|
|
|
|
"mov.w @%2,r2 \n" /* read third word */
|
|
|
|
"swap.b r1,r0 \n" /* swap second word */
|
|
|
|
"mov.w r0,@%0 \n" /* store second word in buf[0] */
|
|
|
|
"cmp/hi %0,%1 \n" /* check for end */
|
|
|
|
"mov.w @%2,r1 \n" /* read fourth word */
|
|
|
|
"swap.b r2,r0 \n" /* swap third word */
|
|
|
|
"mov.w r0,@(2,%0) \n" /* store third word */
|
|
|
|
"bt .loop4_w \n"
|
2004-06-11 06:56:51 +00:00
|
|
|
/* 16 instructions for 4 copies, takes 22 clock cycles (4 wait) */
|
|
|
|
/* avg. 5.5 cycles per word - 118% faster */
|
2004-03-10 14:15:14 +00:00
|
|
|
|
|
|
|
"swap.b r1,r0 \n" /* swap fourth word (last round) */
|
|
|
|
"mov.w r0,@(4,%0) \n" /* and store it */
|
|
|
|
|
2004-04-01 05:46:31 +00:00
|
|
|
".exit: \n"
|
2004-03-10 14:15:14 +00:00
|
|
|
: /* outputs */
|
|
|
|
: /* inputs */
|
|
|
|
/* %0 */ "r"(buf),
|
|
|
|
/* %1 */ "r"(wordcount),
|
|
|
|
/* %2 */ "r"(&ATA_DATA)
|
|
|
|
: /*trashed */
|
|
|
|
"r0","r1","r2","r3"
|
|
|
|
);
|
2004-01-27 09:12:51 +00:00
|
|
|
#endif
|
2004-01-16 09:02:21 +00:00
|
|
|
}
|
|
|
|
|
2002-04-21 22:06:12 +00:00
|
|
|
int ata_read_sectors(unsigned long start,
|
2002-09-25 14:10:50 +00:00
|
|
|
int incount,
|
|
|
|
void* inbuf)
|
2002-04-21 22:06:12 +00:00
|
|
|
{
|
2002-05-16 21:28:21 +00:00
|
|
|
int ret = 0;
|
2002-09-24 14:23:18 +00:00
|
|
|
int timeout;
|
2002-09-25 14:10:50 +00:00
|
|
|
int count;
|
|
|
|
void* buf;
|
2003-04-05 22:25:21 +00:00
|
|
|
int spinup_start;
|
2002-08-27 21:06:48 +00:00
|
|
|
|
|
|
|
mutex_lock(&ata_mtx);
|
|
|
|
|
2002-12-05 09:35:01 +00:00
|
|
|
last_disk_activity = current_tick;
|
2003-04-05 22:25:21 +00:00
|
|
|
spinup_start = current_tick;
|
2002-12-05 09:35:01 +00:00
|
|
|
|
2002-11-27 15:55:47 +00:00
|
|
|
led(true);
|
|
|
|
|
2002-07-16 12:18:17 +00:00
|
|
|
if ( sleeping ) {
|
2002-12-06 15:17:30 +00:00
|
|
|
spinup = true;
|
2002-11-27 15:55:47 +00:00
|
|
|
if (poweroff) {
|
|
|
|
if (ata_power_on()) {
|
|
|
|
mutex_unlock(&ata_mtx);
|
2003-03-31 14:14:07 +00:00
|
|
|
led(false);
|
2002-11-27 15:55:47 +00:00
|
|
|
return -1;
|
|
|
|
}
|
2002-08-02 06:01:22 +00:00
|
|
|
}
|
2002-11-27 15:55:47 +00:00
|
|
|
else {
|
|
|
|
if (perform_soft_reset()) {
|
|
|
|
mutex_unlock(&ata_mtx);
|
2003-03-31 14:14:07 +00:00
|
|
|
led(false);
|
2002-11-27 15:55:47 +00:00
|
|
|
return -1;
|
|
|
|
}
|
2002-07-16 12:18:17 +00:00
|
|
|
}
|
|
|
|
}
|
2002-07-16 14:07:47 +00:00
|
|
|
|
2003-02-27 13:26:09 +00:00
|
|
|
timeout = current_tick + READ_TIMEOUT;
|
|
|
|
|
2002-12-03 13:29:35 +00:00
|
|
|
ATA_SELECT = ata_device;
|
2002-04-21 22:06:12 +00:00
|
|
|
if (!wait_for_rdy())
|
2002-05-16 21:28:21 +00:00
|
|
|
{
|
|
|
|
mutex_unlock(&ata_mtx);
|
2003-03-31 14:14:07 +00:00
|
|
|
led(false);
|
2002-09-05 15:25:08 +00:00
|
|
|
return -2;
|
2002-05-16 21:28:21 +00:00
|
|
|
}
|
2002-04-21 22:06:12 +00:00
|
|
|
|
2003-04-28 12:02:14 +00:00
|
|
|
retry:
|
2002-09-25 14:10:50 +00:00
|
|
|
buf = inbuf;
|
|
|
|
count = incount;
|
2002-09-24 14:23:18 +00:00
|
|
|
while (TIME_BEFORE(current_tick, timeout)) {
|
2003-03-13 15:45:38 +00:00
|
|
|
ret = 0;
|
2003-03-17 13:42:30 +00:00
|
|
|
last_disk_activity = current_tick;
|
2002-09-05 15:25:08 +00:00
|
|
|
|
2002-09-24 14:23:18 +00:00
|
|
|
if ( count == 256 )
|
|
|
|
ATA_NSECTOR = 0; /* 0 means 256 sectors */
|
2002-09-05 15:25:08 +00:00
|
|
|
else
|
2002-09-24 14:23:18 +00:00
|
|
|
ATA_NSECTOR = (unsigned char)count;
|
|
|
|
|
|
|
|
ATA_SECTOR = start & 0xff;
|
|
|
|
ATA_LCYL = (start >> 8) & 0xff;
|
|
|
|
ATA_HCYL = (start >> 16) & 0xff;
|
|
|
|
ATA_SELECT = ((start >> 24) & 0xf) | SELECT_LBA | ata_device;
|
|
|
|
ATA_COMMAND = CMD_READ_MULTIPLE;
|
|
|
|
|
2003-03-31 14:14:07 +00:00
|
|
|
/* wait at least 400ns between writing command and reading status */
|
|
|
|
asm volatile ("nop");
|
|
|
|
asm volatile ("nop");
|
|
|
|
asm volatile ("nop");
|
|
|
|
asm volatile ("nop");
|
|
|
|
asm volatile ("nop");
|
|
|
|
|
2002-09-24 14:23:18 +00:00
|
|
|
while (count) {
|
|
|
|
int sectors;
|
|
|
|
int wordcount;
|
2003-03-14 16:06:09 +00:00
|
|
|
int status;
|
2002-09-24 14:23:18 +00:00
|
|
|
|
|
|
|
if (!wait_for_start_of_transfer()) {
|
2004-03-19 13:26:43 +00:00
|
|
|
/* We have timed out waiting for RDY and/or DRQ, possibly
|
|
|
|
because the hard drive is shaking and has problems reading
|
|
|
|
the data. We have two options:
|
|
|
|
1) Wait some more
|
|
|
|
2) Perform a soft reset and try again.
|
|
|
|
|
|
|
|
We choose alternative 2.
|
|
|
|
*/
|
|
|
|
ata_soft_reset();
|
2002-09-24 14:23:18 +00:00
|
|
|
ret = -4;
|
2002-09-25 14:10:50 +00:00
|
|
|
goto retry;
|
2002-09-24 14:23:18 +00:00
|
|
|
}
|
|
|
|
|
2002-12-06 13:08:42 +00:00
|
|
|
if (spinup) {
|
2003-04-05 22:25:21 +00:00
|
|
|
ata_spinup_time = current_tick - spinup_start;
|
2002-12-06 13:08:42 +00:00
|
|
|
spinup = false;
|
|
|
|
sleeping = false;
|
|
|
|
poweroff = false;
|
|
|
|
}
|
|
|
|
|
2003-03-14 16:06:09 +00:00
|
|
|
/* read the status register exactly once per loop */
|
|
|
|
status = ATA_STATUS;
|
|
|
|
|
2002-09-24 14:23:18 +00:00
|
|
|
/* if destination address is odd, use byte copying,
|
|
|
|
otherwise use word copying */
|
2002-09-05 15:25:08 +00:00
|
|
|
|
2002-09-24 14:23:18 +00:00
|
|
|
if (count >= multisectors )
|
|
|
|
sectors = multisectors;
|
|
|
|
else
|
|
|
|
sectors = count;
|
2002-09-06 16:02:19 +00:00
|
|
|
|
2002-09-24 14:23:18 +00:00
|
|
|
wordcount = sectors * SECTOR_SIZE / 2;
|
|
|
|
|
2004-01-16 09:02:21 +00:00
|
|
|
copy_read_sectors(buf, wordcount);
|
2002-04-27 14:19:00 +00:00
|
|
|
|
2003-03-14 16:06:09 +00:00
|
|
|
/*
|
|
|
|
"Device errors encountered during READ MULTIPLE commands are
|
|
|
|
posted at the beginning of the block or partial block transfer,
|
|
|
|
but the DRQ bit is still set to one and the data transfer shall
|
|
|
|
take place, including transfer of corrupted data, if any."
|
|
|
|
-- ATA specification
|
|
|
|
*/
|
|
|
|
if ( status & (STATUS_BSY | STATUS_ERR | STATUS_DF) ) {
|
2004-03-19 13:26:43 +00:00
|
|
|
ata_soft_reset();
|
2003-03-14 16:06:09 +00:00
|
|
|
ret = -5;
|
|
|
|
goto retry;
|
|
|
|
}
|
|
|
|
|
2002-09-24 14:23:18 +00:00
|
|
|
buf += sectors * SECTOR_SIZE; /* Advance one chunk of sectors */
|
|
|
|
count -= sectors;
|
2002-12-05 09:35:01 +00:00
|
|
|
|
|
|
|
last_disk_activity = current_tick;
|
2002-09-24 14:23:18 +00:00
|
|
|
}
|
2002-04-21 22:06:12 +00:00
|
|
|
|
2003-03-24 16:19:54 +00:00
|
|
|
if(!ret && !wait_for_end_of_transfer()) {
|
2004-03-19 13:26:43 +00:00
|
|
|
ata_soft_reset();
|
2002-09-24 14:23:18 +00:00
|
|
|
ret = -3;
|
2002-09-25 14:10:50 +00:00
|
|
|
goto retry;
|
2002-09-24 14:23:18 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2002-09-05 15:25:08 +00:00
|
|
|
led(false);
|
2002-05-16 21:28:21 +00:00
|
|
|
|
|
|
|
mutex_unlock(&ata_mtx);
|
2002-08-15 12:42:37 +00:00
|
|
|
|
2003-03-13 15:45:38 +00:00
|
|
|
/* only flush if reading went ok */
|
|
|
|
if ( (ret == 0) && delayed_write )
|
2002-08-15 12:42:37 +00:00
|
|
|
ata_flush();
|
|
|
|
|
2002-05-16 21:28:21 +00:00
|
|
|
return ret;
|
2002-04-21 22:06:12 +00:00
|
|
|
}
|
|
|
|
|
2004-04-01 05:46:31 +00:00
|
|
|
/* the tight loop of ata_write_sectors(), to avoid the whole in IRAM */
|
|
|
|
static void copy_write_sectors(unsigned char* buf,
|
|
|
|
int wordcount)
|
|
|
|
__attribute__ ((section (".icode")));
|
|
|
|
|
|
|
|
static void copy_write_sectors(unsigned char* buf, int wordcount)
|
|
|
|
{
|
|
|
|
#ifdef PREFER_C_WRITING
|
|
|
|
|
|
|
|
if ( (unsigned int)buf & 1)
|
|
|
|
{ /* not 16-bit aligned, copy byte by byte */
|
|
|
|
unsigned short tmp = 0;
|
|
|
|
unsigned char* bufend = buf + wordcount*2;
|
|
|
|
do
|
2004-06-11 06:56:51 +00:00
|
|
|
{ /* loop compiles to 9 assembler instructions */
|
|
|
|
/* takes 13 clock cycles (2 pipeline stalls) */
|
|
|
|
tmp = (unsigned short) *buf++;
|
2004-04-01 05:46:31 +00:00
|
|
|
tmp |= (unsigned short) *buf++ << 8; /* I assume big endian */
|
|
|
|
ATA_DATA = tmp; /* and don't use the SWAB16 macro */
|
|
|
|
} while (buf < bufend); /* tail loop is faster */
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{ /* 16-bit aligned, can do faster copy */
|
|
|
|
unsigned short* wbuf = (unsigned short*)buf;
|
|
|
|
unsigned short* wbufend = wbuf + wordcount;
|
|
|
|
do
|
2004-06-11 06:56:51 +00:00
|
|
|
{ /* loop compiles to 6 assembler instructions */
|
|
|
|
/* takes 10 clock cycles (2 pipeline stalls) */
|
2004-04-01 05:46:31 +00:00
|
|
|
ATA_DATA = SWAB16(*wbuf);
|
|
|
|
} while (++wbuf < wbufend); /* tail loop is faster */
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
/* optimized assembler version */
|
|
|
|
/* this assumes wordcount to be a multiple of 2 */
|
|
|
|
|
|
|
|
/* writing is not unrolled as much as reading, for several reasons:
|
|
|
|
* - a similar instruction sequence is faster for writing than for reading
|
|
|
|
* because the auto-incrementing load inctructions can be used
|
|
|
|
* - writing profits from warp mode
|
|
|
|
* Both of these add up to have writing faster than the more unrolled reading.
|
|
|
|
*/
|
|
|
|
asm (
|
|
|
|
"add %1,%1 \n" /* wordcount -> bytecount */
|
|
|
|
"add %0,%1 \n" /* bytecount -> bufend */
|
|
|
|
"mov %0,r0 \n"
|
|
|
|
"tst #1,r0 \n" /* 16-bit aligned ? */
|
|
|
|
"bt .w_aligned \n" /* yes, do word copy */
|
|
|
|
|
|
|
|
/* not 16-bit aligned */
|
|
|
|
"mov #-1,r6 \n" /* prepare a bit mask for high byte */
|
|
|
|
"shll8 r6 \n" /* r6 = 0xFFFFFF00 */
|
|
|
|
|
|
|
|
"mov.b @%0+,r2 \n" /* load (initial old second) first byte */
|
|
|
|
"add #-4,%1 \n" /* adjust end address for early check */
|
|
|
|
"mov.w @%0+,r3 \n" /* load (initial) first word */
|
|
|
|
"bra .w_start2_b \n"
|
|
|
|
"extu.b r2,r0 \n" /* extend unsigned */
|
|
|
|
|
|
|
|
".align 2 \n"
|
|
|
|
".w_loop2_b: \n" /* main loop: copy 2 words in a row */
|
|
|
|
"mov.w @%0+,r3 \n" /* load first word (2+ round) */
|
|
|
|
"extu.b r2,r0 \n" /* put away low byte of second word (2+ round) */
|
|
|
|
"and r6,r2 \n" /* get high byte of second word (2+ round) */
|
|
|
|
"or r1,r2 \n" /* combine with low byte of old first word */
|
|
|
|
"mov.w r2,@%2 \n" /* write that */
|
|
|
|
".w_start2_b: \n"
|
|
|
|
"cmp/hi %0,%1 \n" /* check for end */
|
|
|
|
"mov.w @%0+,r2 \n" /* load second word */
|
|
|
|
"extu.b r3,r1 \n" /* put away low byte of first word */
|
|
|
|
"and r6,r3 \n" /* get high byte of first word */
|
|
|
|
"or r0,r3 \n" /* combine with high byte of old second word */
|
|
|
|
"mov.w r3,@%2 \n" /* write that */
|
|
|
|
"bt .w_loop2_b \n"
|
|
|
|
/* 12 instructions for 2 copies, takes 14 clock cycles */
|
2004-06-11 06:56:51 +00:00
|
|
|
/* avg. 7 cycles per word - 85% faster */
|
2004-04-01 05:46:31 +00:00
|
|
|
|
|
|
|
/* the loop "overreads" 1 byte past the buffer end, however, the last */
|
|
|
|
/* byte is not written to disk */
|
|
|
|
"and r6,r2 \n" /* get high byte of last word */
|
|
|
|
"or r1,r2 \n" /* combine with low byte of old first word */
|
|
|
|
"bra .w_exit \n"
|
|
|
|
"mov.w r2,@%2 \n" /* write last word */
|
|
|
|
|
|
|
|
/* 16-bit aligned, loop(load and write word) */
|
|
|
|
".w_aligned: \n"
|
|
|
|
"mov.w @%0+,r2 \n" /* load first word (1st round) */
|
|
|
|
"bra .w_start2_w \n" /* jump into loop after next instr. */
|
|
|
|
"add #-4,%1 \n" /* adjust end address for early check */
|
|
|
|
|
|
|
|
".align 2 \n"
|
|
|
|
".w_loop2_w: \n" /* main loop: copy 2 words in a row */
|
|
|
|
"mov.w @%0+,r2 \n" /* load first word (2+ round) */
|
|
|
|
"swap.b r1,r0 \n" /* swap second word (2+ round) */
|
|
|
|
"mov.w r0,@%2 \n" /* write second word (2+ round) */
|
|
|
|
".w_start2_w: \n"
|
|
|
|
"cmp/hi %0,%1 \n" /* check for end */
|
|
|
|
"mov.w @%0+,r1 \n" /* load second word */
|
|
|
|
"swap.b r2,r0 \n" /* swap first word */
|
|
|
|
"mov.w r0,@%2 \n" /* write first word */
|
|
|
|
"bt .w_loop2_w \n"
|
|
|
|
/* 8 instructions for 2 copies, takes 10 clock cycles */
|
2004-06-11 06:56:51 +00:00
|
|
|
/* avg. 5 cycles per word - 100% faster */
|
2004-04-01 05:46:31 +00:00
|
|
|
|
|
|
|
"swap.b r1,r0 \n" /* swap second word (last round) */
|
|
|
|
"mov.w r0,@%2 \n" /* and write it */
|
|
|
|
|
|
|
|
".w_exit: \n"
|
|
|
|
: /* outputs */
|
|
|
|
: /* inputs */
|
|
|
|
/* %0 */ "r"(buf),
|
|
|
|
/* %1 */ "r"(wordcount),
|
|
|
|
/* %2 */ "r"(&ATA_DATA)
|
|
|
|
: /*trashed */
|
|
|
|
"r0","r1","r2","r3","r6"
|
|
|
|
);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2002-04-21 22:06:12 +00:00
|
|
|
int ata_write_sectors(unsigned long start,
|
2002-08-14 16:37:28 +00:00
|
|
|
int count,
|
2002-04-22 12:34:25 +00:00
|
|
|
void* buf)
|
2002-04-21 22:06:12 +00:00
|
|
|
{
|
|
|
|
int i;
|
2002-11-07 22:40:24 +00:00
|
|
|
int ret = 0;
|
2003-04-05 22:25:21 +00:00
|
|
|
int spinup_start;
|
2002-08-26 13:21:14 +00:00
|
|
|
|
2002-11-12 20:02:23 +00:00
|
|
|
if (start == 0)
|
|
|
|
panicf("Writing on sector 0\n");
|
|
|
|
|
2002-08-27 21:06:48 +00:00
|
|
|
mutex_lock(&ata_mtx);
|
|
|
|
|
2002-12-05 09:35:01 +00:00
|
|
|
last_disk_activity = current_tick;
|
2003-04-05 22:25:21 +00:00
|
|
|
spinup_start = current_tick;
|
2002-12-05 09:35:01 +00:00
|
|
|
|
2003-03-31 14:14:07 +00:00
|
|
|
led(true);
|
|
|
|
|
2002-08-26 22:05:47 +00:00
|
|
|
if ( sleeping ) {
|
2002-12-06 15:17:30 +00:00
|
|
|
spinup = true;
|
2002-11-27 15:55:47 +00:00
|
|
|
if (poweroff) {
|
|
|
|
if (ata_power_on()) {
|
|
|
|
mutex_unlock(&ata_mtx);
|
2003-03-31 14:14:07 +00:00
|
|
|
led(false);
|
2002-11-27 15:55:47 +00:00
|
|
|
return -1;
|
|
|
|
}
|
2002-08-02 06:01:22 +00:00
|
|
|
}
|
2002-11-27 15:55:47 +00:00
|
|
|
else {
|
|
|
|
if (perform_soft_reset()) {
|
|
|
|
mutex_unlock(&ata_mtx);
|
2003-03-31 14:14:07 +00:00
|
|
|
led(false);
|
2002-11-27 15:55:47 +00:00
|
|
|
return -1;
|
|
|
|
}
|
2002-07-16 12:18:17 +00:00
|
|
|
}
|
2002-08-26 22:05:47 +00:00
|
|
|
}
|
2002-05-16 21:28:21 +00:00
|
|
|
|
2002-12-03 13:29:35 +00:00
|
|
|
ATA_SELECT = ata_device;
|
2002-04-21 22:06:12 +00:00
|
|
|
if (!wait_for_rdy())
|
2002-05-16 21:28:21 +00:00
|
|
|
{
|
|
|
|
mutex_unlock(&ata_mtx);
|
2003-03-31 14:14:07 +00:00
|
|
|
led(false);
|
2002-09-05 15:25:08 +00:00
|
|
|
return -2;
|
2002-05-16 21:28:21 +00:00
|
|
|
}
|
2002-04-21 22:06:12 +00:00
|
|
|
|
2002-08-14 16:37:28 +00:00
|
|
|
if ( count == 256 )
|
|
|
|
ATA_NSECTOR = 0; /* 0 means 256 sectors */
|
|
|
|
else
|
|
|
|
ATA_NSECTOR = (unsigned char)count;
|
2002-04-21 22:06:12 +00:00
|
|
|
ATA_SECTOR = start & 0xff;
|
|
|
|
ATA_LCYL = (start >> 8) & 0xff;
|
|
|
|
ATA_HCYL = (start >> 16) & 0xff;
|
2002-07-02 14:23:30 +00:00
|
|
|
ATA_SELECT = ((start >> 24) & 0xf) | SELECT_LBA | ata_device;
|
2002-04-21 22:06:12 +00:00
|
|
|
ATA_COMMAND = CMD_WRITE_SECTORS;
|
|
|
|
|
|
|
|
for (i=0; i<count; i++) {
|
2004-04-01 05:46:31 +00:00
|
|
|
|
2003-04-28 12:02:14 +00:00
|
|
|
if (!wait_for_start_of_transfer()) {
|
|
|
|
ret = -3;
|
|
|
|
break;
|
2002-05-16 21:28:21 +00:00
|
|
|
}
|
2002-04-21 22:06:12 +00:00
|
|
|
|
2002-12-05 09:35:01 +00:00
|
|
|
if (spinup) {
|
2003-04-05 22:25:21 +00:00
|
|
|
ata_spinup_time = current_tick - spinup_start;
|
2002-12-05 09:35:01 +00:00
|
|
|
spinup = false;
|
2002-12-06 13:08:42 +00:00
|
|
|
sleeping = false;
|
|
|
|
poweroff = false;
|
2002-12-05 09:35:01 +00:00
|
|
|
}
|
|
|
|
|
2004-04-01 05:46:31 +00:00
|
|
|
copy_write_sectors(buf, SECTOR_SIZE/2);
|
2002-04-27 14:19:00 +00:00
|
|
|
|
|
|
|
#ifdef USE_INTERRUPT
|
|
|
|
/* reading the status register clears the interrupt */
|
|
|
|
j = ATA_STATUS;
|
|
|
|
#endif
|
2002-06-12 09:28:22 +00:00
|
|
|
buf += SECTOR_SIZE;
|
2002-12-05 09:35:01 +00:00
|
|
|
|
|
|
|
last_disk_activity = current_tick;
|
2002-04-21 22:06:12 +00:00
|
|
|
}
|
|
|
|
|
2003-04-28 12:02:14 +00:00
|
|
|
if(!ret && !wait_for_end_of_transfer())
|
|
|
|
ret = -4;
|
2002-05-16 21:28:21 +00:00
|
|
|
|
2002-09-23 06:45:46 +00:00
|
|
|
led(false);
|
|
|
|
|
2002-05-16 21:28:21 +00:00
|
|
|
mutex_unlock(&ata_mtx);
|
2002-08-15 12:42:37 +00:00
|
|
|
|
2003-03-13 15:45:38 +00:00
|
|
|
/* only flush if writing went ok */
|
|
|
|
if ( (ret == 0) && delayed_write )
|
2002-08-15 12:42:37 +00:00
|
|
|
ata_flush();
|
|
|
|
|
2002-11-07 22:40:24 +00:00
|
|
|
return ret;
|
2002-04-21 22:06:12 +00:00
|
|
|
}
|
|
|
|
|
2002-08-15 12:42:37 +00:00
|
|
|
extern void ata_delayed_write(unsigned long sector, void* buf)
|
|
|
|
{
|
|
|
|
memcpy(delayed_sector, buf, SECTOR_SIZE);
|
|
|
|
delayed_sector_num = sector;
|
|
|
|
delayed_write = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
extern void ata_flush(void)
|
|
|
|
{
|
|
|
|
if ( delayed_write ) {
|
2002-08-16 14:41:47 +00:00
|
|
|
DEBUGF("ata_flush()\n");
|
2002-08-15 12:42:37 +00:00
|
|
|
delayed_write = false;
|
|
|
|
ata_write_sectors(delayed_sector_num, 1, delayed_sector);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
2002-04-21 22:06:12 +00:00
|
|
|
static int check_registers(void)
|
|
|
|
{
|
2003-07-08 06:33:30 +00:00
|
|
|
if ( ATA_STATUS & STATUS_BSY )
|
2003-07-03 00:02:15 +00:00
|
|
|
return -1;
|
|
|
|
|
2002-04-21 22:06:12 +00:00
|
|
|
ATA_NSECTOR = 0xa5;
|
|
|
|
ATA_SECTOR = 0x5a;
|
|
|
|
ATA_LCYL = 0xaa;
|
|
|
|
ATA_HCYL = 0x55;
|
|
|
|
|
|
|
|
if ((ATA_NSECTOR == 0xa5) &&
|
|
|
|
(ATA_SECTOR == 0x5a) &&
|
|
|
|
(ATA_LCYL == 0xaa) &&
|
|
|
|
(ATA_HCYL == 0x55))
|
2002-05-24 11:25:24 +00:00
|
|
|
return 0;
|
2002-05-16 21:28:21 +00:00
|
|
|
|
2002-05-24 11:25:24 +00:00
|
|
|
return -2;
|
2002-04-21 22:06:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int freeze_lock(void)
|
|
|
|
{
|
2002-12-03 13:29:35 +00:00
|
|
|
ATA_SELECT = ata_device;
|
|
|
|
|
2002-04-21 22:06:12 +00:00
|
|
|
if (!wait_for_rdy())
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
ATA_COMMAND = CMD_SECURITY_FREEZE_LOCK;
|
|
|
|
|
|
|
|
if (!wait_for_rdy())
|
2002-09-05 15:25:08 +00:00
|
|
|
return -2;
|
2002-04-21 22:06:12 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2002-07-16 14:07:47 +00:00
|
|
|
void ata_spindown(int seconds)
|
|
|
|
{
|
|
|
|
sleep_timeout = seconds * HZ;
|
|
|
|
}
|
|
|
|
|
2002-11-29 07:05:27 +00:00
|
|
|
#ifdef HAVE_ATA_POWER_OFF
|
2002-11-28 22:46:19 +00:00
|
|
|
void ata_poweroff(bool enable)
|
|
|
|
{
|
|
|
|
if (enable)
|
|
|
|
poweroff_timeout = 2*HZ;
|
|
|
|
else
|
|
|
|
poweroff_timeout = 0;
|
|
|
|
}
|
2002-11-29 07:05:27 +00:00
|
|
|
#endif
|
2002-11-28 22:46:19 +00:00
|
|
|
|
2002-07-28 15:16:36 +00:00
|
|
|
bool ata_disk_is_active(void)
|
|
|
|
{
|
|
|
|
return !sleeping;
|
|
|
|
}
|
|
|
|
|
2002-07-16 14:07:47 +00:00
|
|
|
static int ata_perform_sleep(void)
|
2002-04-27 14:19:00 +00:00
|
|
|
{
|
2002-05-16 21:28:21 +00:00
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
mutex_lock(&ata_mtx);
|
2002-08-27 21:06:48 +00:00
|
|
|
|
2002-12-03 13:29:35 +00:00
|
|
|
ATA_SELECT = ata_device;
|
|
|
|
|
2002-07-16 14:07:47 +00:00
|
|
|
if(!wait_for_rdy()) {
|
2002-09-02 06:26:00 +00:00
|
|
|
DEBUGF("ata_perform_sleep() - not RDY\n");
|
2002-05-16 21:28:21 +00:00
|
|
|
mutex_unlock(&ata_mtx);
|
2002-04-27 14:19:00 +00:00
|
|
|
return -1;
|
2002-05-16 21:28:21 +00:00
|
|
|
}
|
2002-04-27 14:19:00 +00:00
|
|
|
|
2002-08-02 06:01:22 +00:00
|
|
|
ATA_COMMAND = CMD_SLEEP;
|
2002-04-27 14:19:00 +00:00
|
|
|
|
|
|
|
if (!wait_for_rdy())
|
2002-09-02 06:26:00 +00:00
|
|
|
{
|
|
|
|
DEBUGF("ata_perform_sleep() - CMD failed\n");
|
2002-09-05 15:25:08 +00:00
|
|
|
ret = -2;
|
2002-09-02 06:26:00 +00:00
|
|
|
}
|
2002-11-27 15:55:47 +00:00
|
|
|
|
2002-07-16 14:07:47 +00:00
|
|
|
sleeping = true;
|
2002-05-16 21:28:21 +00:00
|
|
|
mutex_unlock(&ata_mtx);
|
|
|
|
return ret;
|
2002-04-27 14:19:00 +00:00
|
|
|
}
|
|
|
|
|
2003-05-10 01:55:23 +00:00
|
|
|
int ata_standby(int time)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
mutex_lock(&ata_mtx);
|
|
|
|
|
|
|
|
ATA_SELECT = ata_device;
|
|
|
|
|
|
|
|
if(!wait_for_rdy()) {
|
|
|
|
DEBUGF("ata_standby() - not RDY\n");
|
|
|
|
mutex_unlock(&ata_mtx);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2004-02-16 23:25:01 +00:00
|
|
|
if(time)
|
|
|
|
ATA_NSECTOR = ((time + 5) / 5) & 0xff; /* Round up to nearest 5 secs */
|
|
|
|
else
|
|
|
|
ATA_NSECTOR = 0; /* Disable standby */
|
|
|
|
|
2003-05-10 01:55:23 +00:00
|
|
|
ATA_COMMAND = CMD_STANDBY;
|
|
|
|
|
|
|
|
if (!wait_for_rdy())
|
|
|
|
{
|
|
|
|
DEBUGF("ata_standby() - CMD failed\n");
|
|
|
|
ret = -2;
|
|
|
|
}
|
|
|
|
|
|
|
|
mutex_unlock(&ata_mtx);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2002-07-16 12:18:17 +00:00
|
|
|
int ata_sleep(void)
|
|
|
|
{
|
2002-07-16 14:07:47 +00:00
|
|
|
queue_post(&ata_queue, Q_SLEEP, NULL);
|
|
|
|
return 0;
|
|
|
|
}
|
2002-07-16 12:18:17 +00:00
|
|
|
|
2002-08-26 13:21:14 +00:00
|
|
|
void ata_spin(void)
|
|
|
|
{
|
|
|
|
last_user_activity = current_tick;
|
|
|
|
}
|
|
|
|
|
2002-07-16 14:07:47 +00:00
|
|
|
static void ata_thread(void)
|
|
|
|
{
|
2002-11-27 15:55:47 +00:00
|
|
|
static long last_sleep = 0;
|
2002-07-16 14:07:47 +00:00
|
|
|
struct event ev;
|
2002-07-16 12:18:17 +00:00
|
|
|
|
2002-07-16 14:07:47 +00:00
|
|
|
while (1) {
|
2002-08-26 13:21:14 +00:00
|
|
|
while ( queue_empty( &ata_queue ) ) {
|
2002-12-06 15:17:30 +00:00
|
|
|
if ( !spinup && sleep_timeout && !sleeping &&
|
2002-08-26 13:21:14 +00:00
|
|
|
TIME_AFTER( current_tick,
|
|
|
|
last_user_activity + sleep_timeout ) &&
|
|
|
|
TIME_AFTER( current_tick,
|
|
|
|
last_disk_activity + sleep_timeout ) )
|
2002-11-27 15:55:47 +00:00
|
|
|
{
|
2002-08-26 13:21:14 +00:00
|
|
|
ata_perform_sleep();
|
2002-11-27 15:55:47 +00:00
|
|
|
last_sleep = current_tick;
|
|
|
|
}
|
|
|
|
|
2002-12-03 12:02:26 +00:00
|
|
|
#ifdef HAVE_ATA_POWER_OFF
|
2002-12-06 15:17:30 +00:00
|
|
|
if ( !spinup && sleeping && poweroff_timeout && !poweroff &&
|
2002-11-27 15:55:47 +00:00
|
|
|
TIME_AFTER( current_tick, last_sleep + poweroff_timeout ))
|
|
|
|
{
|
|
|
|
mutex_lock(&ata_mtx);
|
|
|
|
ide_power_enable(false);
|
|
|
|
mutex_unlock(&ata_mtx);
|
|
|
|
poweroff = true;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2002-08-26 13:21:14 +00:00
|
|
|
sleep(HZ/4);
|
|
|
|
}
|
2002-07-16 14:07:47 +00:00
|
|
|
queue_wait(&ata_queue, &ev);
|
|
|
|
switch ( ev.id ) {
|
2003-12-12 13:23:33 +00:00
|
|
|
#ifndef USB_NONE
|
2002-07-23 15:02:25 +00:00
|
|
|
case SYS_USB_CONNECTED:
|
2002-11-28 22:46:19 +00:00
|
|
|
if (poweroff) {
|
|
|
|
mutex_lock(&ata_mtx);
|
|
|
|
led(true);
|
2002-11-27 15:55:47 +00:00
|
|
|
ata_power_on();
|
2002-11-28 22:46:19 +00:00
|
|
|
led(false);
|
|
|
|
mutex_unlock(&ata_mtx);
|
|
|
|
}
|
2002-11-27 15:55:47 +00:00
|
|
|
|
2002-07-23 15:02:25 +00:00
|
|
|
/* Tell the USB thread that we are safe */
|
2002-07-27 22:44:52 +00:00
|
|
|
DEBUGF("ata_thread got SYS_USB_CONNECTED\n");
|
2002-07-23 15:02:25 +00:00
|
|
|
usb_acknowledge(SYS_USB_CONNECTED_ACK);
|
2002-07-16 14:07:47 +00:00
|
|
|
|
2002-07-23 15:02:25 +00:00
|
|
|
/* Wait until the USB cable is extracted again */
|
|
|
|
usb_wait_for_disconnect(&ata_queue);
|
|
|
|
break;
|
2003-12-12 13:23:33 +00:00
|
|
|
#endif
|
2002-07-16 14:07:47 +00:00
|
|
|
case Q_SLEEP:
|
2002-09-06 23:55:52 +00:00
|
|
|
last_disk_activity = current_tick - sleep_timeout + (HZ/2);
|
2002-07-16 14:07:47 +00:00
|
|
|
break;
|
|
|
|
}
|
2002-07-16 12:18:17 +00:00
|
|
|
}
|
2002-07-16 14:07:47 +00:00
|
|
|
}
|
2002-07-16 12:18:17 +00:00
|
|
|
|
2002-12-03 11:26:39 +00:00
|
|
|
/* Hardware reset protocol as specified in chapter 9.1, ATA spec draft v5 */
|
2002-04-21 22:06:12 +00:00
|
|
|
int ata_hard_reset(void)
|
|
|
|
{
|
2002-05-16 21:28:21 +00:00
|
|
|
int ret;
|
|
|
|
|
2002-12-03 11:26:39 +00:00
|
|
|
/* state HRR0 */
|
2003-11-07 12:15:24 +00:00
|
|
|
and_b(~0x02, &PADRH); /* assert _RESET */
|
2002-12-03 11:26:39 +00:00
|
|
|
sleep(1); /* > 25us */
|
2002-04-21 22:06:12 +00:00
|
|
|
|
2002-12-03 11:26:39 +00:00
|
|
|
/* state HRR1 */
|
2003-11-07 12:15:24 +00:00
|
|
|
or_b(0x02, &PADRH); /* negate _RESET */
|
2002-12-03 11:26:39 +00:00
|
|
|
sleep(1); /* > 2ms */
|
2002-04-21 22:06:12 +00:00
|
|
|
|
2002-12-03 11:26:39 +00:00
|
|
|
/* state HRR2 */
|
2002-12-03 13:29:35 +00:00
|
|
|
ATA_SELECT = ata_device; /* select the right device */
|
2002-12-02 10:30:40 +00:00
|
|
|
ret = wait_for_bsy();
|
2002-05-16 21:28:21 +00:00
|
|
|
|
2002-06-30 13:10:42 +00:00
|
|
|
/* Massage the return code so it is 0 on success and -1 on failure */
|
|
|
|
ret = ret?0:-1;
|
|
|
|
|
2002-05-16 21:28:21 +00:00
|
|
|
return ret;
|
2002-04-21 22:06:12 +00:00
|
|
|
}
|
|
|
|
|
2002-08-27 21:06:48 +00:00
|
|
|
static int perform_soft_reset(void)
|
2002-04-21 22:06:12 +00:00
|
|
|
{
|
2002-05-16 21:28:21 +00:00
|
|
|
int ret;
|
2002-06-30 13:10:42 +00:00
|
|
|
int retry_count;
|
2002-05-16 21:28:21 +00:00
|
|
|
|
2002-07-02 14:23:30 +00:00
|
|
|
ATA_SELECT = SELECT_LBA | ata_device;
|
2002-04-21 22:06:12 +00:00
|
|
|
ATA_CONTROL = CONTROL_nIEN|CONTROL_SRST;
|
2003-12-17 20:15:12 +00:00
|
|
|
sleep(1); /* >= 5us */
|
2002-04-21 22:06:12 +00:00
|
|
|
|
|
|
|
ATA_CONTROL = CONTROL_nIEN;
|
2003-12-17 20:15:12 +00:00
|
|
|
sleep(1); /* >2ms */
|
2002-08-02 06:01:22 +00:00
|
|
|
|
2002-06-30 13:10:42 +00:00
|
|
|
/* This little sucker can take up to 30 seconds */
|
|
|
|
retry_count = 8;
|
|
|
|
do
|
|
|
|
{
|
2002-07-23 15:02:25 +00:00
|
|
|
ret = wait_for_rdy();
|
2002-06-30 13:10:42 +00:00
|
|
|
} while(!ret && retry_count--);
|
2002-05-16 21:28:21 +00:00
|
|
|
|
2002-06-30 13:10:42 +00:00
|
|
|
/* Massage the return code so it is 0 on success and -1 on failure */
|
|
|
|
ret = ret?0:-1;
|
2002-07-16 12:18:17 +00:00
|
|
|
|
2002-05-16 21:28:21 +00:00
|
|
|
return ret;
|
2002-04-21 22:06:12 +00:00
|
|
|
}
|
|
|
|
|
2002-08-27 21:06:48 +00:00
|
|
|
int ata_soft_reset(void)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
mutex_lock(&ata_mtx);
|
|
|
|
|
|
|
|
ret = perform_soft_reset();
|
|
|
|
|
|
|
|
mutex_unlock(&ata_mtx);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2002-08-02 06:01:22 +00:00
|
|
|
static int ata_power_on(void)
|
|
|
|
{
|
2004-02-17 01:31:50 +00:00
|
|
|
int rc;
|
|
|
|
|
2002-08-02 06:01:22 +00:00
|
|
|
ide_power_enable(true);
|
2002-12-02 10:30:40 +00:00
|
|
|
if( ata_hard_reset() )
|
|
|
|
return -1;
|
2002-08-02 06:01:22 +00:00
|
|
|
|
2004-02-17 01:30:25 +00:00
|
|
|
rc = set_features();
|
|
|
|
if (rc)
|
|
|
|
return rc * 10 - 2;
|
|
|
|
|
2002-12-02 10:30:40 +00:00
|
|
|
if (set_multiple_mode(multisectors))
|
2004-02-17 01:30:25 +00:00
|
|
|
return -3;
|
2002-08-02 06:01:22 +00:00
|
|
|
|
2002-12-03 13:29:35 +00:00
|
|
|
if (freeze_lock())
|
2004-02-17 01:30:25 +00:00
|
|
|
return -4;
|
2002-12-03 13:29:35 +00:00
|
|
|
|
2002-12-02 10:30:40 +00:00
|
|
|
return 0;
|
2002-08-02 06:01:22 +00:00
|
|
|
}
|
|
|
|
|
2002-06-12 13:51:31 +00:00
|
|
|
static int master_slave_detect(void)
|
2002-05-22 14:37:36 +00:00
|
|
|
{
|
|
|
|
/* master? */
|
|
|
|
ATA_SELECT = 0;
|
2003-07-09 22:04:31 +00:00
|
|
|
if ( ATA_STATUS & (STATUS_RDY|STATUS_BSY) ) {
|
2002-07-02 14:23:30 +00:00
|
|
|
ata_device = 0;
|
2002-05-22 14:37:36 +00:00
|
|
|
DEBUGF("Found master harddisk\n");
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
/* slave? */
|
|
|
|
ATA_SELECT = SELECT_DEVICE1;
|
2003-07-09 22:04:31 +00:00
|
|
|
if ( ATA_STATUS & (STATUS_RDY|STATUS_BSY) ) {
|
2002-07-02 14:23:30 +00:00
|
|
|
ata_device = SELECT_DEVICE1;
|
2002-05-22 14:37:36 +00:00
|
|
|
DEBUGF("Found slave harddisk\n");
|
|
|
|
}
|
|
|
|
else
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2002-06-12 13:51:31 +00:00
|
|
|
static int io_address_detect(void)
|
2003-09-01 05:48:42 +00:00
|
|
|
{ /* now, use the HW mask instead of probing */
|
|
|
|
if (read_hw_mask() & ATA_ADDRESS_200)
|
2002-06-12 13:51:31 +00:00
|
|
|
{
|
2002-07-02 14:23:30 +00:00
|
|
|
ata_io_address = 0x200; /* For debug purposes only */
|
2002-06-26 12:36:29 +00:00
|
|
|
old_recorder = false;
|
2002-06-12 13:51:31 +00:00
|
|
|
ata_control = ATA_CONTROL1;
|
|
|
|
}
|
2003-09-01 05:48:42 +00:00
|
|
|
else
|
2002-06-12 13:51:31 +00:00
|
|
|
{
|
2003-09-01 05:48:42 +00:00
|
|
|
ata_io_address = 0x300; /* For debug purposes only */
|
|
|
|
old_recorder = true;
|
|
|
|
ata_control = ATA_CONTROL2;
|
2002-06-12 13:51:31 +00:00
|
|
|
}
|
2003-09-01 05:48:42 +00:00
|
|
|
|
2002-06-12 13:51:31 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2002-06-30 13:10:42 +00:00
|
|
|
void ata_enable(bool on)
|
|
|
|
{
|
|
|
|
if(on)
|
2003-11-07 12:15:24 +00:00
|
|
|
and_b(~0x80, &PADRL); /* enable ATA */
|
2002-06-30 13:10:42 +00:00
|
|
|
else
|
2003-11-07 12:15:24 +00:00
|
|
|
or_b(0x80, &PADRL); /* disable ATA */
|
2002-06-30 13:10:42 +00:00
|
|
|
|
2003-11-07 12:15:24 +00:00
|
|
|
or_b(0x80, &PAIORL);
|
2002-06-30 13:10:42 +00:00
|
|
|
}
|
|
|
|
|
2002-09-05 15:25:08 +00:00
|
|
|
static int identify(void)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2002-12-03 13:29:35 +00:00
|
|
|
ATA_SELECT = ata_device;
|
|
|
|
|
2002-09-05 15:25:08 +00:00
|
|
|
if(!wait_for_rdy()) {
|
|
|
|
DEBUGF("identify() - not RDY\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
ATA_COMMAND = CMD_IDENTIFY;
|
|
|
|
|
|
|
|
if (!wait_for_start_of_transfer())
|
|
|
|
{
|
|
|
|
DEBUGF("identify() - CMD failed\n");
|
|
|
|
return -2;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i=0; i<SECTOR_SIZE/2; i++)
|
|
|
|
/* the IDENTIFY words are already swapped */
|
|
|
|
identify_info[i] = ATA_DATA;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2002-09-06 17:20:44 +00:00
|
|
|
static int set_multiple_mode(int sectors)
|
|
|
|
{
|
2002-12-03 13:29:35 +00:00
|
|
|
ATA_SELECT = ata_device;
|
|
|
|
|
2002-09-06 17:20:44 +00:00
|
|
|
if(!wait_for_rdy()) {
|
|
|
|
DEBUGF("set_multiple_mode() - not RDY\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
ATA_NSECTOR = sectors;
|
|
|
|
ATA_COMMAND = CMD_SET_MULTIPLE_MODE;
|
|
|
|
|
|
|
|
if (!wait_for_rdy())
|
|
|
|
{
|
|
|
|
DEBUGF("set_multiple_mode() - CMD failed\n");
|
|
|
|
return -2;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2004-01-14 13:15:19 +00:00
|
|
|
static int set_features(void)
|
|
|
|
{
|
|
|
|
struct {
|
|
|
|
unsigned char id_word;
|
|
|
|
unsigned char id_bit;
|
|
|
|
unsigned char subcommand;
|
|
|
|
unsigned char parameter;
|
|
|
|
} features[] = {
|
2004-06-11 06:56:51 +00:00
|
|
|
{ 83, 3, 0x05, 0x80 }, /* power management: lowest power without standby */
|
2004-01-14 13:15:19 +00:00
|
|
|
{ 83, 9, 0x42, 0x80 }, /* acoustic management: lowest noise */
|
|
|
|
{ 82, 6, 0xaa, 0 }, /* enable read look-ahead */
|
2004-03-02 09:55:23 +00:00
|
|
|
{ 83, 14, 0x03, 0 }, /* force PIO mode */
|
2004-01-14 13:15:19 +00:00
|
|
|
{ 0, 0, 0, 0 } /* <end of list> */
|
|
|
|
};
|
|
|
|
int i;
|
2004-03-02 09:55:23 +00:00
|
|
|
int pio_mode = 2;
|
|
|
|
|
|
|
|
/* Find out the highest supported PIO mode */
|
|
|
|
if(identify_info[64] & 2)
|
|
|
|
pio_mode = 4;
|
|
|
|
else
|
|
|
|
if(identify_info[64] & 1)
|
|
|
|
pio_mode = 3;
|
2004-01-14 13:15:19 +00:00
|
|
|
|
2004-03-02 09:55:23 +00:00
|
|
|
/* Update the table */
|
|
|
|
features[3].parameter = 8 + pio_mode;
|
|
|
|
|
2004-01-14 13:15:19 +00:00
|
|
|
ATA_SELECT = ata_device;
|
|
|
|
|
|
|
|
if (!wait_for_rdy()) {
|
|
|
|
DEBUGF("set_features() - not RDY\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i=0; features[i].id_word; i++) {
|
|
|
|
if (identify_info[features[i].id_word] & (1 << features[i].id_bit)) {
|
|
|
|
ATA_FEATURE = features[i].subcommand;
|
|
|
|
ATA_NSECTOR = features[i].parameter;
|
|
|
|
ATA_COMMAND = CMD_SET_FEATURES;
|
|
|
|
|
|
|
|
if (!wait_for_rdy()) {
|
|
|
|
DEBUGF("set_features() - CMD failed\n");
|
2004-03-02 09:55:23 +00:00
|
|
|
return -10 - i;
|
|
|
|
}
|
|
|
|
|
|
|
|
if(ATA_ALT_STATUS & STATUS_ERR) {
|
|
|
|
if(ATA_ERROR & ERROR_ABRT) {
|
|
|
|
return -20 - i;
|
|
|
|
}
|
2004-01-14 13:15:19 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2002-12-03 13:12:55 +00:00
|
|
|
unsigned short* ata_get_identify(void)
|
|
|
|
{
|
|
|
|
return identify_info;
|
|
|
|
}
|
|
|
|
|
2002-04-21 22:06:12 +00:00
|
|
|
int ata_init(void)
|
|
|
|
{
|
2003-07-09 22:04:31 +00:00
|
|
|
int rc;
|
|
|
|
bool coldstart = (PACR2 & 0x4000) != 0;
|
2003-07-09 07:18:47 +00:00
|
|
|
|
2003-07-09 22:04:31 +00:00
|
|
|
mutex_init(&ata_mtx);
|
2002-07-16 14:07:47 +00:00
|
|
|
|
2002-05-13 19:22:38 +00:00
|
|
|
led(false);
|
2002-04-21 22:06:12 +00:00
|
|
|
|
2003-07-03 00:02:15 +00:00
|
|
|
/* Port A setup */
|
2003-11-07 12:15:24 +00:00
|
|
|
or_b(0x02, &PAIORH); /* output for ATA reset */
|
|
|
|
or_b(0x02, &PADRH); /* release ATA reset */
|
2003-07-03 00:02:15 +00:00
|
|
|
PACR2 &= 0xBFFF; /* GPIO function for PA7 (IDE enable) */
|
2003-06-26 21:29:13 +00:00
|
|
|
|
2003-07-18 21:55:06 +00:00
|
|
|
sleeping = false;
|
2002-06-30 13:10:42 +00:00
|
|
|
ata_enable(true);
|
2002-04-21 22:06:12 +00:00
|
|
|
|
2002-07-16 14:07:47 +00:00
|
|
|
if ( !initialized ) {
|
2003-12-03 01:03:54 +00:00
|
|
|
if (!ide_powered()) /* somebody has switched it off */
|
|
|
|
{
|
|
|
|
ide_power_enable(true);
|
|
|
|
sleep(HZ); /* allow voltage to build up */
|
|
|
|
}
|
|
|
|
|
2003-07-09 07:18:47 +00:00
|
|
|
if (coldstart)
|
2003-07-08 06:33:30 +00:00
|
|
|
{
|
2004-03-10 14:15:14 +00:00
|
|
|
/* This should reset both master and slave, we don't yet know what's in */
|
2003-07-09 07:18:47 +00:00
|
|
|
ata_device = 0;
|
|
|
|
if (ata_hard_reset())
|
|
|
|
return -1;
|
|
|
|
}
|
2003-07-08 06:33:30 +00:00
|
|
|
|
2003-07-09 16:46:46 +00:00
|
|
|
rc = master_slave_detect();
|
|
|
|
if (rc)
|
2003-07-09 07:18:47 +00:00
|
|
|
return -10 + rc;
|
2003-07-09 16:46:46 +00:00
|
|
|
|
|
|
|
rc = io_address_detect();
|
|
|
|
if (rc)
|
2003-07-09 07:18:47 +00:00
|
|
|
return -20 + rc;
|
|
|
|
|
|
|
|
/* symptom fix: else check_registers() below may fail */
|
|
|
|
if (coldstart && !wait_for_bsy())
|
|
|
|
{
|
|
|
|
return -29;
|
|
|
|
}
|
2002-09-05 15:25:08 +00:00
|
|
|
|
2003-07-09 16:46:46 +00:00
|
|
|
rc = check_registers();
|
|
|
|
if (rc)
|
2003-07-09 07:18:47 +00:00
|
|
|
return -30 + rc;
|
2003-07-09 16:46:46 +00:00
|
|
|
|
|
|
|
rc = freeze_lock();
|
|
|
|
if (rc)
|
2003-07-09 07:18:47 +00:00
|
|
|
return -40 + rc;
|
|
|
|
|
2003-07-09 16:46:46 +00:00
|
|
|
rc = identify();
|
|
|
|
if (rc)
|
2003-07-09 07:18:47 +00:00
|
|
|
return -50 + rc;
|
2002-09-05 15:25:08 +00:00
|
|
|
multisectors = identify_info[47] & 0xff;
|
|
|
|
DEBUGF("ata: %d sectors per ata request\n",multisectors);
|
2002-07-23 15:02:25 +00:00
|
|
|
|
2004-01-14 13:15:19 +00:00
|
|
|
rc = set_features();
|
|
|
|
if (rc)
|
|
|
|
return -60 + rc;
|
|
|
|
|
2002-07-16 14:07:47 +00:00
|
|
|
queue_init(&ata_queue);
|
2003-07-11 19:11:06 +00:00
|
|
|
|
|
|
|
last_disk_activity = current_tick;
|
2002-07-16 14:07:47 +00:00
|
|
|
create_thread(ata_thread, ata_stack,
|
|
|
|
sizeof(ata_stack), ata_thread_name);
|
|
|
|
initialized = true;
|
|
|
|
}
|
2003-07-09 16:46:46 +00:00
|
|
|
rc = set_multiple_mode(multisectors);
|
|
|
|
if (rc)
|
2004-01-14 13:15:19 +00:00
|
|
|
return -70 + rc;
|
2002-05-22 14:37:36 +00:00
|
|
|
|
2002-04-21 22:06:12 +00:00
|
|
|
return 0;
|
|
|
|
}
|