2005-01-28 12:29:21 +00:00
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#include "config.h"
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ENTRY(start)
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2005-07-18 12:40:29 +00:00
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#ifdef CPU_COLDFIRE
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2005-01-28 12:29:21 +00:00
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OUTPUT_FORMAT(elf32-m68k)
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2006-08-31 19:45:05 +00:00
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INPUT(target/coldfire/crt0.o)
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2006-02-05 17:34:49 +00:00
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#elif defined (CPU_ARM)
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2005-11-07 23:07:19 +00:00
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OUTPUT_FORMAT(elf32-littlearm)
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OUTPUT_ARCH(arm)
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2006-10-11 17:47:32 +00:00
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#ifdef CPU_PP
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2006-12-19 11:33:53 +00:00
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INPUT(target/arm/crt0-pp-bl.o)
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2007-11-11 21:07:17 +00:00
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#elif CONFIG_CPU==DM320
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2007-09-30 17:12:20 +00:00
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INPUT(target/arm/tms320dm320/crt0.o)
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2007-11-11 21:06:34 +00:00
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#elif CONFIG_CPU==S3C2440
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INPUT(target/arm/s3c2440/crt0.o)
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2007-10-28 11:08:10 +00:00
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#elif defined(CPU_TCC77X)
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INPUT(target/arm/tcc77x/crt0.o)
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2006-10-11 17:47:32 +00:00
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#else
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2006-08-31 19:45:05 +00:00
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INPUT(target/arm/crt0.o)
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#endif
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2005-01-28 12:29:21 +00:00
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#else
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OUTPUT_FORMAT(elf32-sh)
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2006-08-31 19:45:05 +00:00
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INPUT(target/sh/crt0.o)
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2005-11-07 23:07:19 +00:00
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#endif
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2005-01-28 12:29:21 +00:00
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2005-11-16 23:15:59 +00:00
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#define DRAMSIZE (MEMORYSIZE * 0x100000)
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2005-01-28 12:29:21 +00:00
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2005-07-09 07:46:42 +00:00
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#ifdef IRIVER_H100_SERIES
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2005-04-20 06:48:17 +00:00
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#define DRAMORIG 0x31000000
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2005-01-28 12:29:21 +00:00
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#define IRAMORIG 0x10000000
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#define IRAMSIZE 0x18000
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#define FLASHORIG 0x001f0000
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#define FLASHSIZE 2M
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2005-11-16 23:15:59 +00:00
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#elif defined(IRIVER_H300_SERIES)
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#define DRAMORIG 0x31000000
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#define IRAMORIG 0x10000000
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#define IRAMSIZE 0x18000
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#define FLASHORIG 0x003f0000
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#define FLASHSIZE 4M
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2007-03-04 14:09:21 +00:00
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#elif defined(IAUDIO_X5) || defined(IAUDIO_M5)
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2006-02-04 00:01:15 +00:00
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#define DRAMORIG 0x31000000
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#define IRAMORIG 0x10000000
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#define IRAMSIZE 0x20000
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2006-02-23 10:40:14 +00:00
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#define FLASHORIG 0x00010000
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2006-02-04 00:01:15 +00:00
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#define FLASHSIZE 4M
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2005-11-07 23:07:19 +00:00
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#elif CONFIG_CPU == PP5020
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#define DRAMORIG 0x10000000
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#define IRAMORIG 0x40000000
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#define IRAMSIZE 0x18000
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#define FLASHORIG 0x001f0000
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#define FLASHSIZE 2M
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2007-07-26 21:51:44 +00:00
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#elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
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2006-08-01 22:23:00 +00:00
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#define DRAMORIG 0x10000000
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2007-09-09 11:20:20 +00:00
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#ifndef IRAMORIG
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2006-08-01 22:23:00 +00:00
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#define IRAMORIG 0x40000000
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2007-09-09 11:20:20 +00:00
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#endif
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2007-07-26 21:51:44 +00:00
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#define IRAMSIZE 0x20000
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2006-08-01 22:23:00 +00:00
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#define FLASHORIG 0x001f0000
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#define FLASHSIZE 2M
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2006-02-24 15:42:52 +00:00
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#elif CONFIG_CPU == S3C2440
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#define DRAMORIG 0x30000000
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#define IRAMORIG 0x40000000
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#define IRAMSIZE 4K
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#define FLASHORIG 0x0000000
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#define FLASHSIZE 1M
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2007-09-20 04:46:41 +00:00
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#elif CONFIG_CPU == DM320
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#define DRAMORIG 0x00900000
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#define IRAMORIG 0x00000000
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#define IRAMSIZE 16K
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#define FLASHORIG 0x00100000
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#define FLASHSIZE 8M
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2006-02-05 17:34:49 +00:00
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#elif CONFIG_CPU == PP5002
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#define DRAMORIG 0x28000000
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#define IRAMORIG 0x40000000
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#define IRAMSIZE 0x18000
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#define FLASHORIG 0x001f0000
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#define FLASHSIZE 2M
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2007-09-21 15:51:53 +00:00
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#elif CONFIG_CPU == IMX31L
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#define DRAMORIG 0x80000000
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#define IRAMORIG 0x1FFFC000
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#define IRAMSIZE 16K
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#define FLASHORIG 0x0000000
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#define FLASHSIZE 1M
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2007-10-28 11:08:10 +00:00
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#elif defined(CPU_TCC77X)
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#define DRAMORIG 0x20000000
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#define IRAMORIG 0x00000000
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#define IRAMSIZE 64K
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#define FLASHORIG 0x0000000
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#define FLASHSIZE 1M
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2005-01-28 12:29:21 +00:00
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#else
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#define DRAMORIG 0x09000000
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#define IRAMORIG 0x0f000000
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#define IRAMSIZE 0x1000
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#define FLASHORIG 0x02000000 + ROM_START
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#define FLASHSIZE 256K - ROM_START
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#endif
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2007-10-28 11:08:10 +00:00
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#if defined(CPU_TCC77X)
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MEMORY
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{
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#ifdef TCCBOOT
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DRAM : ORIGIN = DRAMORIG + DRAMSIZE - 0x100000, LENGTH = 0x100000
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#else
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DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
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#endif
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IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
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}
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#elif !defined(CPU_PP) && (CONFIG_CPU!=S3C2440) && (CONFIG_CPU!=IMX31L)
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2005-01-28 12:29:21 +00:00
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MEMORY
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{
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DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
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IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
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FLASH : ORIGIN = FLASHORIG, LENGTH = FLASHSIZE
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}
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2005-11-07 23:07:19 +00:00
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#endif
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2005-01-28 12:29:21 +00:00
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SECTIONS
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2006-08-03 08:41:44 +00:00
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#ifdef CPU_PP
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2005-11-07 23:07:19 +00:00
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{
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. = IRAMORIG;
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2007-11-11 21:06:34 +00:00
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.text : {
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2005-11-07 23:07:19 +00:00
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*(.init.text)
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2007-02-20 11:06:01 +00:00
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*(.text*)
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2005-11-07 23:07:19 +00:00
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}
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2007-10-13 14:53:34 +00:00
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.data : {
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2005-11-07 23:07:19 +00:00
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*(.icode)
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*(.irodata)
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*(.idata)
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2007-02-20 11:06:01 +00:00
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*(.data*)
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2005-11-07 23:07:19 +00:00
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_dataend = . ;
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}
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.stack :
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{
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*(.stack)
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_stackbegin = .;
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stackbegin = .;
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. += 0x2000;
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_stackend = .;
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stackend = .;
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}
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2005-11-13 20:59:30 +00:00
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/* The bss section is too large for IRAM - we just move it 16MB into the
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DRAM */
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2005-11-07 23:07:19 +00:00
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2005-11-13 20:59:30 +00:00
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. = (DRAMORIG+16*1024*1024);
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2005-11-07 23:07:19 +00:00
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.bss : {
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2005-11-20 01:58:56 +00:00
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_edata = .;
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2007-02-20 11:06:01 +00:00
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*(.bss*);
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2005-11-07 23:07:19 +00:00
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*(.ibss);
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2005-11-20 01:58:56 +00:00
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_end = .;
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2005-11-07 23:07:19 +00:00
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}
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}
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2006-08-12 08:27:48 +00:00
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#elif (CONFIG_CPU==S3C2440)
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{
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2007-09-20 04:46:41 +00:00
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. = DRAMORIG + 0x1000000;
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.text : {
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*(.init.text)
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*(.text*)
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}
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.data : {
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*(.icode)
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*(.irodata)
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*(.idata)
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*(.data*)
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. = ALIGN(0x4);
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_dataend = . ;
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}
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.stack :
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{
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*(.stack)
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_stackbegin = .;
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stackbegin = .;
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. += 0x2000;
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_stackend = .;
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stackend = .;
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}
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.bss : {
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_edata = .;
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*(.bss*);
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*(.ibss);
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2007-09-30 22:21:51 +00:00
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*(COMMON)
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2007-09-20 04:46:41 +00:00
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_end = .;
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}
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}
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2007-10-28 11:08:10 +00:00
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#elif defined(CPU_TCC77X)
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{
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.text : {
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*(.init.text)
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*(.text)
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*(.text*)
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*(.glue_7)
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*(.glue_7t)
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} > DRAM
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.data : {
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*(.icode)
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*(.irodata)
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*(.idata)
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*(.data*)
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*(.rodata.*)
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. = ALIGN(0x4);
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_dataend = . ;
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} > DRAM
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.stack :
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{
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*(.stack)
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_stackbegin = .;
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stackbegin = .;
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. += 0x2000;
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_stackend = .;
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stackend = .;
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} > DRAM
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.bss : {
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_edata = .;
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*(.bss*);
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*(.ibss);
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*(COMMON)
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_end = .;
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} > DRAM
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}
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2007-09-20 04:46:41 +00:00
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#elif (CONFIG_CPU==DM320)
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{
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. = DRAMORIG + 0x1000000;
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.text : {
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2007-10-13 14:53:34 +00:00
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loadaddress = .;
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_loadaddress = .;
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2007-09-20 04:46:41 +00:00
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*(.init.text)
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*(.text*)
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*(.glue_7)
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*(.glue_7t)
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. = ALIGN(0x4);
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} > DRAM
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.rodata :
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{
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*(.rodata) /* problems without this, dunno why */
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*(.rodata*)
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*(.rodata.str1.1)
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*(.rodata.str1.4)
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. = ALIGN(0x4);
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/* Pseudo-allocate the copies of the data sections */
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_datacopy = .;
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} > DRAM
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.data : {
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*(.icode)
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*(.irodata)
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*(.idata)
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*(.data*)
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. = ALIGN(0x4);
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_dataend = . ;
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2007-10-13 14:53:34 +00:00
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} > DRAM
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2007-09-20 04:46:41 +00:00
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.stack :
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{
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*(.stack)
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_stackbegin = .;
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stackbegin = .;
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. += 0x2000;
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_stackend = .;
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stackend = .;
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2007-10-13 14:53:34 +00:00
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} > DRAM
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2007-09-22 06:04:14 +00:00
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2007-10-13 14:53:34 +00:00
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.bss :
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{
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2007-09-20 04:46:41 +00:00
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_edata = .;
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*(.bss*);
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*(.ibss);
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2007-09-30 22:21:51 +00:00
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*(COMMON)
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2007-09-20 04:46:41 +00:00
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_end = .;
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2007-10-13 14:53:34 +00:00
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} > DRAM
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2007-09-30 22:21:51 +00:00
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2007-10-13 14:53:34 +00:00
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.vectors IRAMORIG :
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2007-09-22 06:04:14 +00:00
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{
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_vectorsstart = .;
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KEEP(*(.resetvectors));
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*(.resetvectors);
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KEEP(*(.vectors));
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*(.vectors);
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_vectorsend = .;
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2007-10-13 14:53:34 +00:00
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} AT > DRAM
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2007-09-22 06:04:14 +00:00
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_vectorscopy = LOADADDR(.vectors);
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2006-08-12 08:27:48 +00:00
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}
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2007-09-21 15:51:53 +00:00
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#elif (CONFIG_CPU==IMX31L)
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{
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. = 0x88201000;
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.vectors :
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{
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KEEP(*(.vectors*));
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*(.vectors*);
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}
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.text : {
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*(.init.text)
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*(.text*)
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}
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.data : {
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*(.icode)
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*(.irodata)
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*(.idata)
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*(.data*)
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_dataend = . ;
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}
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.stack :
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{
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*(.stack)
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_stackbegin = .;
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stackbegin = .;
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. += 0x2000;
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_stackend = .;
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stackend = .;
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}
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.bss : {
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_edata = .;
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*(.bss*);
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*(.ibss);
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_end = .;
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}
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}
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2005-11-07 23:07:19 +00:00
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#else
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2005-01-28 12:29:21 +00:00
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{
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.vectors :
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{
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2007-03-04 14:09:21 +00:00
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#if defined(IAUDIO_X5) || defined(IAUDIO_M5)
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2006-02-23 10:40:14 +00:00
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*(.init.text)
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#endif
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2005-01-28 12:29:21 +00:00
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_datacopy = .;
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} > FLASH
|
|
|
|
|
|
|
|
.data : AT ( _datacopy )
|
|
|
|
{
|
|
|
|
_datastart = .;
|
2007-02-22 00:01:20 +00:00
|
|
|
KEEP(*(.resetvectors));
|
2005-01-28 12:29:21 +00:00
|
|
|
*(.resetvectors);
|
2007-02-22 00:01:20 +00:00
|
|
|
KEEP(*(.vectors));
|
2005-01-28 12:29:21 +00:00
|
|
|
*(.vectors);
|
|
|
|
. = ALIGN(0x200);
|
|
|
|
*(.icode)
|
2005-10-19 19:35:24 +00:00
|
|
|
*(.irodata)
|
2005-01-28 12:29:21 +00:00
|
|
|
*(.idata)
|
2007-02-20 11:06:01 +00:00
|
|
|
*(.data*)
|
2005-01-28 12:29:21 +00:00
|
|
|
. = ALIGN(0x4);
|
2007-09-20 04:46:41 +00:00
|
|
|
_dataend = .;
|
2005-01-28 12:29:21 +00:00
|
|
|
. = ALIGN(0x10); /* Maintain proper alignment for .text section */
|
|
|
|
} > IRAM
|
2007-09-20 04:46:41 +00:00
|
|
|
|
2005-01-28 12:29:21 +00:00
|
|
|
/* TRICK ALERT! Newer versions of the linker don't allow output sections
|
|
|
|
to overlap even if one of them is empty, so advance the location pointer
|
|
|
|
"by hand" */
|
|
|
|
.text LOADADDR(.data) + SIZEOF(.data) :
|
|
|
|
{
|
|
|
|
*(.init.text)
|
2007-02-20 11:06:01 +00:00
|
|
|
*(.text*)
|
2005-01-28 12:29:21 +00:00
|
|
|
. = ALIGN(0x4);
|
|
|
|
} > FLASH
|
|
|
|
|
|
|
|
.rodata :
|
|
|
|
{
|
2007-02-20 11:06:01 +00:00
|
|
|
*(.rodata*)
|
2005-01-28 12:29:21 +00:00
|
|
|
. = ALIGN(0x4);
|
|
|
|
_iramcopy = .;
|
|
|
|
} > FLASH
|
|
|
|
|
|
|
|
.stack :
|
|
|
|
{
|
|
|
|
*(.stack)
|
|
|
|
_stackbegin = .;
|
|
|
|
stackbegin = .;
|
|
|
|
. += 0x2000;
|
|
|
|
_stackend = .;
|
|
|
|
stackend = .;
|
|
|
|
} > IRAM
|
|
|
|
|
2007-03-04 14:09:21 +00:00
|
|
|
#if defined(IRIVER_H100_SERIES) || defined(IRIVER_H300_SERIES) \
|
|
|
|
|| defined(IAUDIO_X5) || defined(IAUDIO_M5)
|
2005-12-06 17:37:32 +00:00
|
|
|
.bss DRAMORIG+0x800000:
|
2005-11-16 23:15:59 +00:00
|
|
|
#else
|
2005-01-28 12:29:21 +00:00
|
|
|
.bss :
|
2005-11-16 23:15:59 +00:00
|
|
|
#endif
|
2005-01-28 12:29:21 +00:00
|
|
|
{
|
|
|
|
_edata = .;
|
2005-10-19 19:35:24 +00:00
|
|
|
*(.ibss)
|
2007-02-20 11:06:01 +00:00
|
|
|
*(.bss*)
|
2005-01-28 12:29:21 +00:00
|
|
|
*(COMMON)
|
|
|
|
_end = .;
|
2007-03-04 14:09:21 +00:00
|
|
|
#if defined(IRIVER_H100_SERIES) || defined(IRIVER_H300_SERIES) \
|
|
|
|
|| defined(IAUDIO_X5) || defined(IAUDIO_M5)
|
2005-11-16 23:15:59 +00:00
|
|
|
} > DRAM
|
|
|
|
#else
|
2005-01-28 12:29:21 +00:00
|
|
|
} > IRAM
|
2005-11-16 23:15:59 +00:00
|
|
|
#endif
|
2005-01-28 12:29:21 +00:00
|
|
|
|
|
|
|
}
|
2005-11-07 23:07:19 +00:00
|
|
|
#endif
|