2002-03-27 09:25:09 +00:00
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#define _PAGE_ Jukebox notes
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#include "head.t"
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<h2>Exception vectors</h2>
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<p>The first 0x200 bytes of the image appears to be the exception vector table.
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The vectors are explained on pages 54 and 70-71 in the SH-1 Hardware Manual,
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<p>Here's the vector table for v5.03a:
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<table border=1><tr>
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<th>Vector</th><th>Address</th><th>Description/interrupt source</th>
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<tr><td> 0</td><td>09000200</td><td>Power-on reset PC</td></tr>
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<tr><td> 1</td><td>0903f2bc</td><td>Power-on reset SP</td></tr>
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<tr><td> 2</td><td>09000200</td><td>Manual reset PC</td></tr>
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<tr><td> 3</td><td>0903f2bc</td><td>Manual reset SP</td></tr>
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<tr><td> 11</td><td>09000cac</td><td>NMI</td></tr>
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<tr><td> 64</td><td>0900c060</td><td>IRQ0</td></tr>
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<tr><td> 70</td><td>09004934</td><td>IRQ6</td></tr>
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<tr><td> 78</td><td>09004a38</td><td>DMAC3 DEI3</td></tr>
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<tr><td> 80</td><td>0900dfd0</td><td>ITU0 IMIA0</td></tr>
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<tr><td> 88</td><td>0900df60</td><td>ITU2 IMIA2</td></tr>
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<tr><td> 90</td><td>0900df60</td><td>ITU2 OVI2</td></tr>
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<tr><td>104</td><td>09004918</td><td>SCI1 ERI1</td></tr>
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<tr><td>105</td><td>090049e0</td><td>SCI1 Rxl1</td></tr>
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<tr><td>109</td><td>09010270</td><td>A/D ITI</td></tr>
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</table>
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<p>From the use of address 0x0903f2bc as stack pointer, we can deduce
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that the DRAM is located at address 0x09000000.
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This is backed by the HW manual p102, which says that DRAM can only be at put on CS1, which is either 0x01000000 (8-bit) or 0x09000000 (16-bit).
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<p>The vector table also corresponds with the fact that there is code at address 0x200 of the image file. 0x200 is thus the starting point for all code.
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<h2>Port pins</h2>
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<p><table><tr valign="top"><td>
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<p>Port A pin function configuration summary:
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<table border=1>
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<tr><th>Pin</th><th>Function</th><th>Input/output</th><th>Initial value</th><th>Used for</th></tr>
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<tr><td>PA0</td><td>i/o</td><td>Input</td><td></td><td>DC adapter detect</td></tr>
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<tr><td>PA1</td><td>/RAS</td><td>Output</td><td></td><td>DRAM</td></tr>
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<tr><td>PA2</td><td>/CS6</td><td>Output</td><td></td><td>IDE</td></tr>
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<tr><td>PA3</td><td>/WAIT</td></tr>
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<tr><td>PA4</td><td>/WR</td><td>Output</td><td></td><td>DRAM+Flash</td></tr>
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<tr><td>PA5</td><td>i/o</td><td>Input</td><td></td><td>Key: ON</td></tr>
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<tr><td>PA6</td><td>/RD</td><td>Output</td><td></td><td>IDE</td></tr>
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<tr><td>PA7</td><td>i/o</td><td>Output</td><td>0</td></tr>
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<tr><td>PA8</td><td>i/o</td><td>Output</td><td>0</td></tr>
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<tr><td>PA9</td><td>i/o</td><td>Output</td><td>1</td></tr>
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<tr><td>PA10</td><td>i/o</td><td>Output</td></tr>
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<tr><td>PA11</td><td>i/o</td><td>Input</td><td></td><td>Key: STOP</td></tr>
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<tr><td>PA12</td><td>/IRQ0</td></tr>
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<tr><td>PA13</td><td>i/o</td></tr>
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<tr><td>PA14</td><td>i/o</td></tr>
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<tr><td>PA15</td><td>i/o</td><td>Input</td><td></td><td>USB cable detect</td></tr>
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</table>
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</td><td>
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<p>Port B pin function configuration summary:
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<table border=1>
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<tr><th>Pin</th><th>Function</th><th>Input/output</th><th>Initial value</th><th>Used for</th></tr>
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<tr><td>PB0</td><td>i/o</td><td>Output</td><td></td><td>LCD</td></tr>
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<tr><td>PB1</td><td>i/o</td><td>Output</td><td></td><td>LCD</td></tr>
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<tr><td>PB2</td><td>i/o</td><td>Output</td><td></td><td>LCD</td></tr>
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<tr><td>PB3</td><td>i/o</td><td>Output</td><td></td><td>LCD</td></tr>
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<tr><td>PB4</td><td>i/o</td><td>Input</td></tr>
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2002-04-22 11:51:37 +00:00
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<tr><td>PB5</td><td>i/o</td><td>Output</td><td>1</td><td>MAS WSEN</td></tr>
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2002-03-27 09:25:09 +00:00
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<tr><td>PB6</td><td>i/o</td><td>Output</td><td>0</td></tr>
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2002-04-22 11:51:37 +00:00
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<tr><td>PB7</td><td>i/o</td><td>Output</td><td></td><td>I<EFBFBD>C data</td></tr>
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2002-03-27 09:25:09 +00:00
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<tr><td>PB8</td><td>i/o</td></tr>
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<tr><td>PB9</td><td>TxD0</td><td>Output</td><td></td><td>MPEG</td></tr>
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<tr><td>PB10</td><td>RxD1</td><td>Input</td></td><td></td><td>Remote</td></tr>
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<tr><td>PB11</td><td>TxD1</td><td>Output</td><td></td><td>Remote?</td></tr>
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<tr><td>PB12</td><td>SCK0</td><td>Output</td><td></td><td>MPEG</td></tr>
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2002-04-22 11:51:37 +00:00
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<tr><td>PB13</td><td>i/o</td><td>Output</td><td></td><td>I<EFBFBD>C clock</td></tr>
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2002-05-03 08:29:15 +00:00
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<tr><td>PB14</td><td>/IRQ6</td><td>Input</td><td></td><td>MAS demand</td></tr>
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<tr><td>PB15</td><td>i/o</td><td>Input</td><td></td><td>MAS MP3 frame sync</td></tr>
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2002-03-27 09:25:09 +00:00
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</table>
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</td></tr></table>
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<p>Port C pin function configuration summary:
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<table border=1>
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<tr><th>Pin</th><th>Function</th><th>Input/output</th><th>Used for</th></tr>
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<tr><td>PC0</td><td>i/o</td><td>Input</td><td>Key: - / PREV</td></tr>
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<tr><td>PC1</td><td>i/o</td><td>Input</td><td>Key: MENU</td></tr>
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<tr><td>PC2</td><td>i/o</td><td>Input</td><td>Key: + / NEXT</td></tr>
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<tr><td>PC3</td><td>i/o</td><td>Input</td><td>Key: PLAY</td></tr>
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<tr><td>PC4</td><td>i/o</td><td>Input</td></tr>
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<tr><td>PC5</td><td>i/o</td><td>Input</td></tr>
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<tr><td>PC6</td><td>i/o</td><td>Input</td></tr>
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<tr><td>PC7</td><td>i/o</td><td>Input</td></tr>
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</table>
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<h2>Labels</h2>
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<p>Note: Everything is about v5.03a.
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<ul>
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<li>0x0200: Start point
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<li>0x383d: Text: "Archos Jukebox hard drive is not bootable! Please insert a bootable floppy and press any key to try again" :-)
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<li>0xc390: Address of "Update" string shown early on LCD.
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<li>0xc8c0: Start of setup code
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<li>0xc8c8: DRAM setup
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<li>0xc4a0: Serial port 1 setup
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<li>0xc40a: Port configuration setup
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<li>0xe3bc: Character set conversion table
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<li>0xfcd0: ITU setup
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<li>0xc52a: Memory area #6 setup
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<li>0x114b0: Start of menu strings
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</ul>
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<h2>Setup</h2>
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<p>The startup code at 0x200 (0x09000200) naturally begins with setting up the system.
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<h3>Vector Base Register</h3>
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<p>The first thing the code does is setting the VBR, Vector Base Register,
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and thus move the exception vector table from the internal ROM at address 0
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to the DRAM at address 0x09000000:
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<pre>
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0x00000200: mov.l @(0x02C,pc),r1 ; 0x0000022C (0x09000000)
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0x00000202: ldc r1,vbr
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</pre>
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<h3>Stack</h3>
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<p>The next instruction loads r15 with the contents of 0x228, which is 0x0903f2bc. This is the stack pointer, which is used all over the code.
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<pre>
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0x00000204: mov.l @(0x024,pc),r15 ; 0x00000228 (0x0903F2BC)
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</pre>
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<p>After that the code jumps to the hardware setup at 0xc8c0.
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<pre>
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0x00000206: mov.l @(0x01C,pc),r0 ; 0x00000220 (0x0900C8C0)
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0x00000208: jsr @r0
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</pre>
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<h3>DRAM controller</h3>
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<p>First up is DRAM setup, at 0xc8c8. It sets the memory controller registers:
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<pre>
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0x0000C8C8: mov.l @(0x068,pc),r2 ; 0x0000C930 (0x05FFFFA8)
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0x0000C8CA: mov.w @(0x05A,pc),r1 ; 0x0000C924 (0x1E00)
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0x0000C8CC: mov.l @(0x068,pc),r7 ; 0x0000C934 (0x0F0001C0)
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0x0000C8CE: mov.w r1,@r2 ; 0x1e00 -> DCR
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0x0000C8D0: mov.l @(0x068,pc),r2 ; 0x0000C938 (0x05FFFFAC)
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0x0000C8D2: mov.w @(0x054,pc),r1 ; 0x0000C926 (0x5AB0)
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0x0000C8D4: mov.w r1,@r2 ; 0x5ab0 -> RCR
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0x0000C8D6: mov.l @(0x068,pc),r2 ; 0x0000C93C (0x05FFFFB2)
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0x0000C8D8: mov.w @(0x050,pc),r1 ; 0x0000C928 (0x9605)
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0x0000C8DA: mov.w r1,@r2 ; 0x9505 -> RTCOR
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0x0000C8DC: mov.l @(0x064,pc),r2 ; 0x0000C940 (0x05FFFFAE)
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0x0000C8DE: mov.w @(0x04C,pc),r1 ; 0x0000C92A (0xA518)
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0x0000C8E0: mov.w r1,@r2 ; 0xa518 -> RTCSR
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</pre>
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<h3>Serial port 0</h3>
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<p>Code starting at 0x483c.
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<p>As C code:
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<table border><tr><td bgcolor="#a0d6e8">
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<pre>
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void setup_sci0(void)
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{
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/* set PB12 to output */
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PBIOR |= 0x1000;
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/* Disable serial port */
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SCR0 = 0x00;
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/* Syncronous, 8N1, no prescale */
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SMR0 = 0x80;
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/* Set baudrate 1Mbit/s */
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BRR0 = 0x03;
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/* use SCK as serial clock output */
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SCR0 = 0x01;
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/* Clear FER and PER */
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SSR0 &= 0xe7;
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/* Set interrupt D priority to 0 */
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IPRD &= 0x0ff0;
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/* set IRQ6 and IRQ7 to edge detect */
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ICR |= 0x03;
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/* set PB15 and PB14 to inputs */
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PBIOR &= 0x7fff;
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PBIOR &= 0xbfff;
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/* set IRQ6 prio 8 and IRQ7 prio 0 */
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IPRB = ( IPRB & 0xff00 ) | 0x80;
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/* Enable Tx (only!) */
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SCR0 = 0x20;
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}
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</pre>
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</td></tr></table>
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<h3>Serial port 1</h3>
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<p>Code starting at 0x47a0.
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<p>As C code:
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<table border><tr><td bgcolor="#a0d6e8">
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<pre>
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#define SYSCLOCK 12000000
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#define PRIORITY 8
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void setup_sci1(int baudrate)
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{
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/* Disable serial port */
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SCR1 = 0;
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/* Set PB11 to Tx and PB10 to Rx */
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PBCR1 = (PBCR1 & 0xff0f) | 0xa0;
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/* Asynchronous, 8N1, no prescaler */
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|
|
|
SMR1 = 0;
|
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|
|
|
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|
|
/* Set baudrate */
|
|
|
|
|
|
BRR1 = SYSCLOCK / (baudrate * 32) - 1;
|
|
|
|
|
|
|
|
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|
|
/* Clear FER and PER */
|
|
|
|
|
|
SSR1 &= 0xe7;
|
|
|
|
|
|
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|
|
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|
|
/* Set interrupt priority to 8 */
|
|
|
|
|
|
IPRE = (IPRE & 0x0fff) | (PRIORITY << 12);
|
|
|
|
|
|
|
|
|
|
|
|
/* Enable Rx, Tx and Rx interrupt */
|
|
|
|
|
|
SCR1 = 0x70;
|
|
|
|
|
|
}
|
|
|
|
|
|
</pre>
|
|
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|
|
</td></tr></table>
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|
|
<h3>Pin configuration</h3>
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|
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<p>Starting at 0xc40a:
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<p><tt>CASCR = 0xafff</tt>: Column Address Strobe Pin Control Register. Set bits CASH MD1 and CASL MD1.
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<h4>Port A</h4>
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<br><tt>PACR1 = 0x0102</tt>: Set pin functions
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<br><tt>PACR2 = 0xbb98</tt>: Set pin functions
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<br><tt>PAIOR &= 0xfffe</tt>: PA0 is input
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<br><tt>PAIOR &= 0xffdf</tt>: PA5 is input
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<br><tt>PADR &= 0xff7f</tt>: Set pin PA7 low
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<br><tt>PAIOR |= 0x80</tt>: PA7 is output
|
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<br><tt>PAIOR |= 0x100</tt>: PA8 is output
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<br><tt>PADR |= 0x200</tt>: Set pin PA9 high
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<br><tt>PAIOR |= 0x200</tt>: PA9 is output
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<br><tt>PAIOR |= 0x400</tt>: PA10 is output
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<br><tt>PAIOR &= 0xf7ff</tt>: PA11 is input
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<br><tt>PAIOR &= 0xbfff</tt>: PA14 is input
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<br><tt>PAIOR = 0x7fff</tt>: PA15 is input
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<br><tt>PADR &= 0xfeff</tt>: Set pin PA8 low
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<h4>Port B</h4>
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<br><tt>PBCR1 = 0x12a8</tt>: Set pin functions
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|
<br><tt>PBCR2 = 0x0000</tt>: Set pin functions
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|
<br><tt>PBDR &= 0xffef</tt>: Set pin PB4 low
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|
|
<br><tt>PBIOR &= 0xffef</tt>: PB4 is input
|
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|
<br><tt>PBIOR |= 0x20</tt>: PB5 is output
|
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|
|
<br><tt>PBIOR |= 0x40</tt>: PA6 is output
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|
<br><tt>PBDR &= 0xffbf</tt>: Set pin PB6 low
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|
<br><tt>PBDR |= 0x20</tt>: Set pin PB5 high
|
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|
|
<h3>ITU (Integrated Timer Pulse Unit)</h3>
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|
|
<p>Starting at 0xfcd0:
|
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|
|
<p><tt>TSNC &= 0xfe</tt>: The timer counter for channel 0 (TCNT0) operates independently of other channels
|
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|
|
<br><tt>TMDR &= 0xfe</tt>: Channel 0 operates in normal (not PWM) mode
|
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|
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|
|
<br><tt>GRA0 = 0x1d4c</tt>:
|
|
|
|
|
|
<br><tt>TCR0 &= 0x67; TCR0 |= 0x23</tt>: TCNT is cleared by general register A (GRA) compare match or input capture. Counter clock = f/8
|
|
|
|
|
|
<br><tt>TIOR0 = 0x88</tt>: Compare disabled
|
|
|
|
|
|
<br><tt>TIER0 = 0xf9</tt>: Enable interrupt requests by IMFA (IMIA)
|
|
|
|
|
|
<br><tt>IPRC &= 0xff0f; IPRC |= 0x30</tt>: Set ITU0 interrupt priority level 3.
|
|
|
|
|
|
<br><tt>TSTR |= 0x01</tt>: Start TCNT0
|
|
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|
|
|
|
|
|
|
|
|
<h3>Memory area #6 ?</h3>
|
|
|
|
|
|
|
|
|
|
|
|
<p>From 0xc52a:
|
|
|
|
|
|
|
|
|
|
|
|
<p><tt>PADR |= 0x0200</tt>: Set PA13 high
|
|
|
|
|
|
<br><tt>WCR1 = 0x40ff</tt>: Enable /WAIT support for memory area 6. Hmmm, what's on CS6?
|
|
|
|
|
|
<br><tt>WCR1 &= 0xfdfd</tt>: Turn off RW5 (was off already) and WW1 (enable short address output cycle).
|
|
|
|
|
|
<br><tt>WCR3 &= 0xe7ff</tt>: Turn off A6LW1 and A6LW0; 1 wait state for CS6.
|
|
|
|
|
|
<br><tt>ICR |= 0x80</tt>: Interrupt is requested on falling edge of IRQ0 input
|
|
|
|
|
|
|
|
|
|
|
|
<h2>Remote control</h2>
|
|
|
|
|
|
<p>Tjerk Schuringa reports:
|
|
|
|
|
|
"Finally got that extra bit going on my bitpattern generator. So far I fed only
|
|
|
|
|
|
simple characters to my jukebox, and this is the result:
|
|
|
|
|
|
|
|
|
|
|
|
<pre>
|
|
|
|
|
|
START D0 1 2 3 4 5 6 7 STOP FUNCTION
|
|
|
|
|
|
0 0 0 0 0 0 1 1 1 1 VOL- (the one I got already)
|
|
|
|
|
|
0 0 0 0 1 0 1 1 VOL+ (figures)
|
|
|
|
|
|
0 0 0 1 0 0 1 1 +
|
|
|
|
|
|
0 0 1 0 0 0 1 1 -
|
|
|
|
|
|
0 1 0 0 0 0 1 1 STOP
|
|
|
|
|
|
1 0 0 0 0 0 1 1 PLAY
|
|
|
|
|
|
</pre>
|
|
|
|
|
|
|
|
|
|
|
|
<p>I also found that "repeat" functions (keep a button depressed) needs to be
|
|
|
|
|
|
faster than 0.5 s. If it is around 1 second or more it is interpreted as a
|
|
|
|
|
|
seperate keypress. So far I did not get the "fast forward" function because the
|
|
|
|
|
|
fastest I can get is 0.5 s.
|
|
|
|
|
|
|
|
|
|
|
|
<p>Very important: the baudrate is indeed 9600 baud! These pulses are fed to the
|
|
|
|
|
|
second ring on the headphone jack, and (if I understood correctly) go to RxD1
|
|
|
|
|
|
of the SH1."
|
|
|
|
|
|
|
|
|
|
|
|
<h2>LCD display</h2>
|
|
|
|
|
|
|
|
|
|
|
|
<p>The Recorder uses a Shing Yih Technology G112064-30<EFBFBD>graphic LCD display with 112x64 pixels. The controller is a Solomon SSD1815Z.
|
|
|
|
|
|
|
|
|
|
|
|
<p>It's not yet known what display/controller the Jukebox has, but I'd be surprised if it doesn't use a similar controller.
|
|
|
|
|
|
|
|
|
|
|
|
<p>Starting at 0xE050, the code flicks PB2 and PB3 a great deal and then some with PB1 and PB0. Which gives us the following connections:
|
|
|
|
|
|
|
|
|
|
|
|
<table border><tr><th>CPU pin</th><th>LCD pin</th></tr>
|
|
|
|
|
|
<tr><td>PB0</td><td>DC</td></tr>
|
|
|
|
|
|
<tr><td>PB1</td><td>CS1</td></tr>
|
|
|
|
|
|
<tr><td>PB2</td><td>SCK</td></tr>
|
|
|
|
|
|
<tr><td>PB3</td><td>SDA</td></tr>
|
|
|
|
|
|
</table>
|
|
|
|
|
|
|
|
|
|
|
|
<p>The Recorder apparently has the connections this way (according to Gary Czvitkovicz):
|
|
|
|
|
|
<table border><tr><th>CPU pin</th><th>LCD pin</th></tr>
|
|
|
|
|
|
<tr><td>PB0</td><td>SDA</td></tr>
|
|
|
|
|
|
<tr><td>PB1</td><td>SCK</td></tr>
|
|
|
|
|
|
<tr><td>PB2</td><td>DC</td></tr>
|
|
|
|
|
|
<tr><td>PB3</td><td>CS1</td></tr>
|
|
|
|
|
|
</table>
|
|
|
|
|
|
|
2002-04-11 13:58:49 +00:00
|
|
|
|
<a name="charsets"><p>The player charsets:
|
2002-03-27 09:25:09 +00:00
|
|
|
|
|
|
|
|
|
|
<p><table border=0><tr>
|
|
|
|
|
|
<td><img src="codes_old.png" width=272 height=272><br>
|
|
|
|
|
|
<small>Old LCD charset (before v4.50)</small></td>
|
|
|
|
|
|
<td><img src="codes_new.png" width=272 height=272><br>
|
|
|
|
|
|
<small>New LCD charset (after v4.50)</small></td></tr></table>
|
|
|
|
|
|
|
2002-04-11 13:58:49 +00:00
|
|
|
|
<p>And the Recorder charset looks like this:
|
|
|
|
|
|
<br>
|
|
|
|
|
|
<img src="codes_rec.png">
|
2002-03-27 09:25:09 +00:00
|
|
|
|
|
|
|
|
|
|
<h3>Code</h3>
|
|
|
|
|
|
|
|
|
|
|
|
<p>This C snippet write a byte to the Jukebox LCD controller.
|
|
|
|
|
|
The 'data' flag inticates if the byte is a command byte or a data byte.
|
|
|
|
|
|
|
|
|
|
|
|
<table border><tr><td bgcolor="#a0d6e8">
|
|
|
|
|
|
<pre>
|
|
|
|
|
|
#define DC 1
|
|
|
|
|
|
#define CS1 2
|
|
|
|
|
|
#define SDA 4
|
|
|
|
|
|
#define SCK 8
|
|
|
|
|
|
|
|
|
|
|
|
void lcd_write(int byte, int data)
|
|
|
|
|
|
{
|
|
|
|
|
|
int i;
|
|
|
|
|
|
char on,off;
|
|
|
|
|
|
|
|
|
|
|
|
PBDR &= ~CS1; /* enable lcd chip select */
|
|
|
|
|
|
|
|
|
|
|
|
if ( data ) {
|
|
|
|
|
|
on=~(SDA|SCK);
|
|
|
|
|
|
off=SCK|DC;
|
|
|
|
|
|
}
|
|
|
|
|
|
else {
|
|
|
|
|
|
on=~(SDA|SCK|DC);
|
|
|
|
|
|
off=SCK;
|
|
|
|
|
|
}
|
|
|
|
|
|
/* clock out each bit, MSB first */
|
|
|
|
|
|
for (i=0x80;i;i>>=1)
|
|
|
|
|
|
{
|
|
|
|
|
|
PBDR &= on;
|
|
|
|
|
|
if (i & byte)
|
|
|
|
|
|
PBDR |= SDA;
|
|
|
|
|
|
PBDR |= off;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
PBDR |= CS1; /* disable lcd chip select */
|
|
|
|
|
|
}
|
|
|
|
|
|
</pre>
|
|
|
|
|
|
</td></tr></table>
|
|
|
|
|
|
|
|
|
|
|
|
<h2>Firmware size</h2>
|
|
|
|
|
|
|
|
|
|
|
|
<p>Joachim Schiffer found out that firmware files have to be at least 51200
|
|
|
|
|
|
bytes to be loaded by newer firmware ROMs.
|
|
|
|
|
|
So my "first program" only works on players with older firmware in ROM
|
|
|
|
|
|
(my has 3.18). Joachim posted a
|
|
|
|
|
|
<a href="mail/jukebox-archive-2001-12/att-0087/01-AJBREC.ajz">padded version</a> that works everywhere.
|
|
|
|
|
|
|
2002-04-11 13:58:49 +00:00
|
|
|
|
<p>Tests have shown that firmware sizes above 200K won't load.
|
|
|
|
|
|
|
2002-03-27 09:25:09 +00:00
|
|
|
|
#include "foot.t"
|
