2003-12-12 13:29:34 +00:00
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#include "config.h"
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2002-05-02 14:05:51 +00:00
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ENTRY(start)
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2005-07-18 12:40:29 +00:00
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#ifdef CPU_COLDFIRE
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2004-10-06 13:30:44 +00:00
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OUTPUT_FORMAT(elf32-m68k)
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2006-08-31 19:45:05 +00:00
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INPUT(target/coldfire/crt0.o)
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2005-02-10 15:25:16 +00:00
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#elif CONFIG_CPU == TCC730
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OUTPUT_FORMAT(elf32-calmrisc16)
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2005-11-07 23:07:19 +00:00
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INPUT(crt0.o)
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2006-01-12 00:35:50 +00:00
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#elif defined(CPU_ARM)
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2005-11-07 23:07:19 +00:00
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OUTPUT_FORMAT(elf32-littlearm)
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OUTPUT_ARCH(arm)
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2006-08-31 19:45:05 +00:00
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#ifdef CPU_PP
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INPUT(target/arm/crt0-pp.o)
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#elif defined(CPU_ARM)
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INPUT(target/arm/crt0.o)
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#endif
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2004-10-06 13:30:44 +00:00
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#else
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2002-03-28 15:09:10 +00:00
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OUTPUT_FORMAT(elf32-sh)
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2006-08-31 19:45:05 +00:00
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INPUT(target/sh/crt0.o)
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2005-11-07 23:07:19 +00:00
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#endif
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2002-08-01 08:12:17 +00:00
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2005-02-10 22:37:09 +00:00
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#if CONFIG_CPU == TCC730
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MEMORY
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{
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FIRMWARE : ORIGIN = LOADADDRESS, LENGTH = 256K
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FLASH (RX) : ORIGIN = 0x000000, LENGTH = 1024K
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ICMEM (RX) : ORIGIN = 0x3FC000, LENGTH = 32K
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IMEM1 : ORIGIN = 0x200000, LENGTH = 32K
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2005-03-07 15:29:37 +00:00
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IMEM2 : ORIGIN = 0x210000, LENGTH = 16K
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IMEM3 : ORIGIN = 0x220000, LENGTH = 32K
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2005-02-10 22:37:09 +00:00
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IMEM4 : ORIGIN = 0x230000, LENGTH = 16K
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DRAM : ORIGIN = 0x000000, LENGTH = 0x3F0000
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}
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SECTIONS
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{
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.text LOADADDRESS : {
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*(.init.text)
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*(.text)
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}> FLASH AT> FIRMWARE
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.icode 0x3FC040: {
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*(.vectors)
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2005-03-07 15:29:37 +00:00
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*(.icode)
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2005-02-10 22:37:09 +00:00
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}> ICMEM AT> FIRMWARE
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2005-02-11 18:42:57 +00:00
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/* We start at 0x2000, to avoid overwriting Archos' loader datasegment.
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* If it turns out that we won't call back the loader, this can be set to 0.
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*/
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.bss 0x2000 : {
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*(.bss)
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. = ALIGN(2);
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}> DRAM
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2005-02-10 22:37:09 +00:00
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2005-02-11 18:42:57 +00:00
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/* Data is put after BSS, to have all strings addresses > VIRT_PTR + VIRT_SIZE.
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Strings are in rodata, so what we really assert is (.rodata > VIRT_PTR + VIRT_SIZE)
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See settings.h for details */
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.data ALIGN(2): {
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2005-02-10 22:37:09 +00:00
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*(.data)
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. = ALIGN(2);
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*(.rodata)
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. = ALIGN(2);
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*(.rodata.str1.2)
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. = ALIGN(2);
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}> DRAM AT> FIRMWARE
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.stack ALIGN(2) : {
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. = . + 0x2000;
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}> DRAM
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.idata 0x200000: {
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*(.idata)
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2005-02-25 09:12:44 +00:00
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}> IMEM1
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2005-02-10 22:37:09 +00:00
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2005-03-07 15:29:37 +00:00
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.idata2 0x220000: {
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2005-02-25 09:12:44 +00:00
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*(.idata2)
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2005-03-07 15:29:37 +00:00
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}> IMEM3
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2005-02-10 22:37:09 +00:00
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_codesize = SIZEOF(.text);
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_icodecopy = LOADADDR(.icode);
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_icodestart = ADDR(.icode);
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_icodesize = SIZEOF(.icode);
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_datacopy = LOADADDR(.data);
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_datastart = ADDR(.data);
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_datasize = SIZEOF(.data);
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_bssstart = ADDR(.bss);
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_bsssize = (SIZEOF(.bss) + 1) & ~ 1;
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_stackbegin = ADDR(.stack);
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_stackend = ADDR(.stack) + SIZEOF(.stack);
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_idatastart = ADDR(.idata);
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2005-04-05 11:33:58 +00:00
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/* FIXME: Where to put audio buffer? */
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2005-02-11 10:25:15 +00:00
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2005-04-05 11:33:58 +00:00
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_audiobuffer = 0;
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2005-05-24 15:38:46 +00:00
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_audiobufend = 0;
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2005-02-11 10:25:15 +00:00
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/* Plugins are not supported on the Gmini*/
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_pluginbuf = 0;
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2005-11-07 23:07:19 +00:00
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}
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2005-02-10 22:37:09 +00:00
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#else
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2005-06-27 21:23:03 +00:00
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#define PLUGINSIZE PLUGIN_BUFFER_SIZE
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#define CODECSIZE CODEC_SIZE
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2003-06-29 16:33:04 +00:00
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2005-06-22 02:47:54 +00:00
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2003-02-26 16:05:30 +00:00
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#ifdef DEBUG
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2004-10-06 13:30:44 +00:00
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#define STUBOFFSET 0x10000
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2003-02-26 16:05:30 +00:00
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#else
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2004-10-06 13:30:44 +00:00
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#define STUBOFFSET 0
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2003-02-26 16:05:30 +00:00
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#endif
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2004-10-06 13:30:44 +00:00
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2005-06-22 02:47:54 +00:00
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#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - STUBOFFSET - CODECSIZE
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2003-02-26 09:18:13 +00:00
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2005-07-09 07:46:42 +00:00
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#if defined(IRIVER_H100_SERIES) || defined(IRIVER_H300)
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2005-07-08 15:08:59 +00:00
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#define DRAMORIG 0x31000000 + STUBOFFSET
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2005-07-09 07:46:42 +00:00
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#define IRAMORIG 0x10000000
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2005-09-01 20:57:33 +00:00
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#define IRAMSIZE 0xc000
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2006-03-18 23:06:45 +00:00
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#elif defined(IAUDIO_X5)
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#define DRAMORIG 0x31000000 + STUBOFFSET
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#define IRAMORIG 0x10000000
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2006-04-11 10:37:37 +00:00
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#define IRAMSIZE 0x14000
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2006-02-05 17:34:49 +00:00
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#elif (CONFIG_CPU==PP5002) || (CONFIG_CPU==PP5020)
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2005-12-12 13:21:08 +00:00
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#define DRAMORIG 0x00000000 + STUBOFFSET
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2005-11-12 15:29:43 +00:00
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#define IRAMORIG 0x40000000
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#define IRAMSIZE 0xc000
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2006-01-12 00:35:50 +00:00
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#elif CONFIG_CPU==PNX0101
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2006-02-12 23:16:05 +00:00
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#define DRAMORIG 0xc00000 + STUBOFFSET
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2006-01-24 23:32:53 +00:00
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#define IRAMORIG 0x400000
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2006-08-12 22:43:44 +00:00
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#define IRAMSIZE 0x7000
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2006-02-24 15:42:52 +00:00
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#elif CONFIG_CPU==S3C2440
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#define DRAMORIG 0x30000000 + STUBOFFSET
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#define IRAMORIG 0x40000000
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#define IRAMSIZE 4K
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2004-10-06 13:30:44 +00:00
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#else
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#define DRAMORIG 0x09000000 + STUBOFFSET
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#define IRAMORIG 0x0f000000
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#define IRAMSIZE 0x1000
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#endif
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2005-06-22 02:47:54 +00:00
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/* End of the audio buffer, where the codec buffer starts */
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#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
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/* Where the codec buffer ends, and the plugin buffer starts */
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#define ENDADDR (ENDAUDIOADDR + CODECSIZE)
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2004-10-06 13:48:25 +00:00
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2002-08-01 08:12:17 +00:00
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MEMORY
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{
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2004-10-06 13:30:44 +00:00
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DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
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IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
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2006-08-12 21:03:23 +00:00
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#if CONFIG_CPU==PNX0101
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IRAM0 : ORIGIN = 0x0, LENGTH = IRAMSIZE
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#endif
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2002-08-01 08:12:17 +00:00
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}
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2002-03-28 15:09:10 +00:00
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SECTIONS
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{
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2006-01-24 23:32:53 +00:00
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#ifndef CPU_ARM
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2002-08-01 08:12:17 +00:00
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.vectors :
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2002-03-28 15:09:10 +00:00
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{
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2005-03-31 08:47:02 +00:00
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loadaddress = .;
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_loadaddress = .;
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2005-06-21 00:01:28 +00:00
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KEEP(*(.resetvectors));
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2002-05-29 09:12:34 +00:00
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*(.resetvectors);
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2005-06-21 00:01:28 +00:00
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KEEP(*(.vectors));
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2002-03-28 15:09:10 +00:00
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*(.vectors);
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2002-08-01 08:12:17 +00:00
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} > DRAM
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2002-05-02 14:05:51 +00:00
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.text :
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{
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2006-01-24 23:32:53 +00:00
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#else
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.text :
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{
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loadaddress = .;
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_loadaddress = .;
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#endif
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2004-07-24 17:56:38 +00:00
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. = ALIGN(0x200);
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*(.init.text)
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2005-06-21 00:01:28 +00:00
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*(.text*)
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2006-01-12 00:35:50 +00:00
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#ifdef CPU_ARM
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2005-11-12 15:29:43 +00:00
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*(.glue_7)
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*(.glue_7t)
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#endif
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2003-04-24 20:25:10 +00:00
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. = ALIGN(0x4);
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2002-08-01 08:12:17 +00:00
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} > DRAM
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2002-03-28 15:09:10 +00:00
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2004-07-24 17:56:38 +00:00
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.rodata :
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2002-05-02 14:05:51 +00:00
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{
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2005-06-21 00:01:28 +00:00
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*(.rodata) /* problems without this, dunno why */
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*(.rodata*)
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2004-10-07 08:37:25 +00:00
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*(.rodata.str1.1)
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2004-07-24 17:56:38 +00:00
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*(.rodata.str1.4)
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2004-01-28 20:43:31 +00:00
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. = ALIGN(0x4);
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2004-07-24 17:56:38 +00:00
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/* Pseudo-allocate the copies of the data sections */
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_datacopy = .;
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2002-08-01 08:12:17 +00:00
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} > DRAM
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2002-05-02 14:05:51 +00:00
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2004-07-24 17:56:38 +00:00
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/* TRICK ALERT! For RAM execution, we put the .data section at the
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same load address as the copy. Thus, we don't waste extra RAM
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when we don't actually need the copy. */
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.data : AT ( _datacopy )
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2002-05-02 14:05:51 +00:00
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{
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2004-07-24 17:56:38 +00:00
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_datastart = .;
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2005-06-21 00:01:28 +00:00
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*(.data*)
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2003-04-24 20:25:10 +00:00
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. = ALIGN(0x4);
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2004-07-24 17:56:38 +00:00
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_dataend = .;
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2002-08-01 08:12:17 +00:00
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} > DRAM
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2002-05-24 15:37:26 +00:00
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2005-07-24 15:32:28 +00:00
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/DISCARD/ :
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{
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*(.eh_frame)
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}
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2006-01-24 23:32:53 +00:00
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#ifdef CPU_ARM
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.vectors 0x0 :
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{
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_vectorsstart = .;
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*(.vectors);
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_vectorsend = .;
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2006-08-12 21:03:23 +00:00
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#if CONFIG_CPU==PNX0101
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*(.dmabuf)
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} >IRAM0 AT> DRAM
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#else
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2006-01-24 23:32:53 +00:00
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} AT> DRAM
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2006-08-12 21:03:23 +00:00
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#endif
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2006-01-24 23:32:53 +00:00
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_vectorscopy = LOADADDR(.vectors);
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#endif
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#if CONFIG_CPU==PNX0101
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.iram IRAMORIG + SIZEOF(.vectors) :
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#else
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.iram IRAMORIG :
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#endif
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2004-07-24 17:56:38 +00:00
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{
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_iramstart = .;
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*(.icode)
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2005-10-19 19:35:24 +00:00
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*(.irodata)
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2004-07-24 17:56:38 +00:00
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*(.idata)
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_iramend = .;
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2006-01-24 23:32:53 +00:00
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} > IRAM AT> DRAM
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_iramcopy = LOADADDR(.iram);
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2005-10-19 19:35:24 +00:00
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.ibss (NOLOAD) :
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{
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_iedata = .;
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*(.ibss)
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. = ALIGN(0x4);
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_iend = .;
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} > IRAM
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2004-07-24 17:56:38 +00:00
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2006-01-12 00:35:50 +00:00
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#if defined(CPU_COLDFIRE) || defined(CPU_ARM)
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2005-03-01 12:25:30 +00:00
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.stack :
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{
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*(.stack)
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stackbegin = .;
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2005-09-01 20:57:33 +00:00
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. += 0x2000;
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2005-03-01 12:25:30 +00:00
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stackend = .;
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} > IRAM
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2006-08-03 16:29:42 +00:00
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2006-08-03 16:44:45 +00:00
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#ifdef CPU_PP
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2006-08-03 16:29:42 +00:00
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.cop_stack :
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{
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*(.cop_stack)
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cop_stackbegin = .;
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. += 0x0500;
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cop_stackend = .;
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} > IRAM
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2006-08-03 16:44:45 +00:00
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#endif
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2006-08-03 16:29:42 +00:00
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2005-03-01 12:25:30 +00:00
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#else
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2004-07-24 17:56:38 +00:00
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/* TRICK ALERT! We want 0x2000 bytes of stack, but we set the section
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size smaller, and allow the stack to grow into the .iram copy */
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2004-08-09 21:35:57 +00:00
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.stack ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram):
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2002-05-24 15:37:26 +00:00
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{
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*(.stack)
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2004-08-09 21:35:57 +00:00
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_stackbegin = . - SIZEOF(.iram);
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. += 0x2000 - SIZEOF(.iram);
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2002-07-15 22:15:00 +00:00
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_stackend = .;
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2002-08-01 08:12:17 +00:00
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} > DRAM
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2005-03-01 12:25:30 +00:00
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#endif
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2002-05-24 15:37:26 +00:00
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2006-01-24 23:32:53 +00:00
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#if defined(CPU_COLDFIRE)
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2005-03-01 12:25:30 +00:00
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.bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram):
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2006-01-24 23:32:53 +00:00
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#elif defined(CPU_ARM)
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.bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors):
|
2005-03-01 12:25:30 +00:00
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#else
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2002-08-01 08:58:17 +00:00
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.bss :
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2005-03-01 12:25:30 +00:00
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#endif
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2002-08-01 08:58:17 +00:00
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{
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_edata = .;
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2005-06-21 00:01:28 +00:00
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*(.bss*)
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2002-08-01 08:58:17 +00:00
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*(COMMON)
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2005-03-18 07:53:52 +00:00
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. = ALIGN(0x4);
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2002-08-01 08:58:17 +00:00
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_end = .;
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} > DRAM
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2005-04-05 11:33:58 +00:00
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.audiobuf ALIGN(4) :
|
2002-05-24 15:37:26 +00:00
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{
|
2005-04-05 11:33:58 +00:00
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_audiobuffer = .;
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audiobuffer = .;
|
2002-08-01 08:12:17 +00:00
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} > DRAM
|
2002-05-24 15:37:26 +00:00
|
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2005-06-22 02:47:54 +00:00
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.audiobufend ENDAUDIOADDR:
|
2002-05-24 15:37:26 +00:00
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{
|
2005-04-05 11:33:58 +00:00
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audiobufend = .;
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_audiobufend = .;
|
2002-08-01 08:12:17 +00:00
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} > DRAM
|
2002-03-28 15:09:10 +00:00
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|
2005-06-22 02:47:54 +00:00
|
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.codec ENDAUDIOADDR:
|
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{
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codecbuf = .;
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_codecbuf = .;
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}
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|
2003-06-29 16:33:04 +00:00
|
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.plugin ENDADDR:
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{
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_pluginbuf = .;
|
2005-02-03 08:36:18 +00:00
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pluginbuf = .;
|
2003-06-29 16:33:04 +00:00
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}
|
2002-05-24 15:37:26 +00:00
|
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}
|
2005-02-10 22:37:09 +00:00
|
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#endif
|