2011-11-06 22:44:25 +00:00
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id: s5l8700.h 28791 2010-12-11 09:39:33Z Buschel $
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*
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* Copyright (C) 2008 by Marcoen Hirschberg, Bart van Adrichem
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __S5L8702_H__
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#define __S5L8702_H__
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#include <inttypes.h>
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#define REG8_PTR_T volatile uint8_t *
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#define REG16_PTR_T volatile uint16_t *
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#define REG32_PTR_T volatile uint32_t *
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2014-11-10 00:50:19 +00:00
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#define CACHEALIGN_BITS (5) /* 2^5 = 32 bytes */
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2011-11-06 22:44:25 +00:00
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#define DRAM_ORIG 0x08000000
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2015-12-17 01:37:18 +00:00
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#define IRAM_ORIG 0x22000000
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2011-11-06 22:44:25 +00:00
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#define DRAM_SIZE (MEMORYSIZE * 0x100000)
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#define IRAM_SIZE 0x40000
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2015-12-17 01:37:18 +00:00
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#define TTB_SIZE 0x4000
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#define TTB_BASE_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE)
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2011-11-06 22:44:25 +00:00
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2015-09-25 23:35:15 +00:00
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#define IRAM0_ORIG 0x22000000
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#define IRAM0_SIZE 0x20000
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#define IRAM1_ORIG 0x22020000
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#define IRAM1_SIZE 0x20000
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2011-11-06 22:44:25 +00:00
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/////SYSTEM CONTROLLER/////
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#define CLKCON0 (*((volatile uint32_t*)(0x3C500000)))
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#define CLKCON1 (*((volatile uint32_t*)(0x3C500004)))
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#define CLKCON2 (*((volatile uint32_t*)(0x3C500008)))
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#define CLKCON3 (*((volatile uint32_t*)(0x3C50000C)))
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#define CLKCON4 (*((volatile uint32_t*)(0x3C500010)))
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#define CLKCON5 (*((volatile uint32_t*)(0x3C500014)))
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#define PLL0PMS (*((volatile uint32_t*)(0x3C500020)))
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#define PLL1PMS (*((volatile uint32_t*)(0x3C500024)))
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#define PLL2PMS (*((volatile uint32_t*)(0x3C500028)))
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#define PLL0LCNT (*((volatile uint32_t*)(0x3C500030)))
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#define PLL1LCNT (*((volatile uint32_t*)(0x3C500034)))
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#define PLL2LCNT (*((volatile uint32_t*)(0x3C500038)))
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#define PLLLOCK (*((volatile uint32_t*)(0x3C500040)))
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#define PLLMODE (*((volatile uint32_t*)(0x3C500044)))
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#define PWRCON(i) (*((uint32_t volatile*)(0x3C500000 \
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+ ((i) == 4 ? 0x6C : \
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((i) == 3 ? 0x68 : \
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((i) == 2 ? 0x58 : \
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((i) == 1 ? 0x4C : \
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0x48)))))))
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2015-12-17 01:37:18 +00:00
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/* SW Reset Control Register */
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#define SWRCON (*((volatile uint32_t*)(0x3C500050)))
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/* Reset Status Register */
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#define RSTSR (*((volatile uint32_t*)(0x3C500054)))
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#define RSTSR_WDR_BIT (1 << 2)
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#define RSTSR_SWR_BIT (1 << 1)
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#define RSTSR_HWR_BIT (1 << 0)
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/////WATCHDOG/////
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#define WDTCON (*((volatile uint32_t*)(0x3C800000)))
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#define WDTCNT (*((volatile uint32_t*)(0x3C800004)))
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/////MEMCONTROLLER/////
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#define MIU_BASE (0x38100000)
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#define MIU_REG(off) (*((uint32_t volatile*)(MIU_BASE + (off))))
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/* following registers are similar to s5l8700x */
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#define MIUCON (*((uint32_t volatile*)(0x38100000)))
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#define MIUCOM (*((uint32_t volatile*)(0x38100004)))
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#define MIUAREF (*((uint32_t volatile*)(0x38100008)))
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#define MIUMRS (*((uint32_t volatile*)(0x3810000C)))
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#define MIUSDPARA (*((uint32_t volatile*)(0x38100010)))
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2011-11-06 22:44:25 +00:00
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/////TIMER/////
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2014-11-10 01:39:16 +00:00
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/* 16/32-bit timers:
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*
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* - Timers A..D: 16-bit counter, very similar to 16-bit timers described
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* in S5L8700 DS, it seems that the timers C and D are disabled or not
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* implemented.
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*
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* - Timers E..H: 32-bit counter, they are like 16-bit timers, but the
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* interrupt status for all 32-bit timers is located in TSTAT register.
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*
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* - Clock source configuration:
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*
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* TCON[10:8] (Tx_CS) TCON[6]=0 TCON[6]=1
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* ------------------ --------- ---------
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* 000 PCLK / 2 ECLK / 2
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* 001 PCLK / 4 ECLK / 4
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* 010 PCLK / 16 ECLK / 16
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* 011 PCLK / 64 ECLK / 64
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* 10x (timers E..H) PCLK ECLK
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* 10x (timers A..D) Ext. Clock 0 Ext. Clock 0
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* 11x Ext. Clock 1 Ext. Clock 1
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*
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* On Classic:
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* - Ext. Clock 0: not connected or disabled
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* - Ext. Clock 1: 32768 Hz, external OSC1?, PMU?
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* - ECLK: 12 MHz, external OSC0?
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*/
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#define TIMER_FREQ 12000000 /* ECLK */
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2011-11-06 22:44:25 +00:00
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#define TACON (*((uint32_t volatile*)(0x3C700000)))
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#define TACMD (*((uint32_t volatile*)(0x3C700004)))
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#define TADATA0 (*((uint32_t volatile*)(0x3C700008)))
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#define TADATA1 (*((uint32_t volatile*)(0x3C70000C)))
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#define TAPRE (*((uint32_t volatile*)(0x3C700010)))
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#define TACNT (*((uint32_t volatile*)(0x3C700014)))
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#define TBCON (*((uint32_t volatile*)(0x3C700020)))
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#define TBCMD (*((uint32_t volatile*)(0x3C700024)))
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#define TBDATA0 (*((uint32_t volatile*)(0x3C700028)))
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#define TBDATA1 (*((uint32_t volatile*)(0x3C70002C)))
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#define TBPRE (*((uint32_t volatile*)(0x3C700030)))
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#define TBCNT (*((uint32_t volatile*)(0x3C700034)))
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#define TCCON (*((uint32_t volatile*)(0x3C700040)))
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#define TCCMD (*((uint32_t volatile*)(0x3C700044)))
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#define TCDATA0 (*((uint32_t volatile*)(0x3C700048)))
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#define TCDATA1 (*((uint32_t volatile*)(0x3C70004C)))
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#define TCPRE (*((uint32_t volatile*)(0x3C700050)))
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#define TCCNT (*((uint32_t volatile*)(0x3C700054)))
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#define TDCON (*((uint32_t volatile*)(0x3C700060)))
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#define TDCMD (*((uint32_t volatile*)(0x3C700064)))
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#define TDDATA0 (*((uint32_t volatile*)(0x3C700068)))
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#define TDDATA1 (*((uint32_t volatile*)(0x3C70006C)))
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#define TDPRE (*((uint32_t volatile*)(0x3C700070)))
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#define TDCNT (*((uint32_t volatile*)(0x3C700074)))
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#define TECON (*((uint32_t volatile*)(0x3C7000A0)))
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#define TECMD (*((uint32_t volatile*)(0x3C7000A4)))
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#define TEDATA0 (*((uint32_t volatile*)(0x3C7000A8)))
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#define TEDATA1 (*((uint32_t volatile*)(0x3C7000AC)))
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#define TEPRE (*((uint32_t volatile*)(0x3C7000B0)))
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#define TECNT (*((uint32_t volatile*)(0x3C7000B4)))
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#define TFCON (*((uint32_t volatile*)(0x3C7000C0)))
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#define TFCMD (*((uint32_t volatile*)(0x3C7000C4)))
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#define TFDATA0 (*((uint32_t volatile*)(0x3C7000C8)))
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#define TFDATA1 (*((uint32_t volatile*)(0x3C7000CC)))
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#define TFPRE (*((uint32_t volatile*)(0x3C7000D0)))
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#define TFCNT (*((uint32_t volatile*)(0x3C7000D4)))
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#define TGCON (*((uint32_t volatile*)(0x3C7000E0)))
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#define TGCMD (*((uint32_t volatile*)(0x3C7000E4)))
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#define TGDATA0 (*((uint32_t volatile*)(0x3C7000E8)))
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#define TGDATA1 (*((uint32_t volatile*)(0x3C7000EC)))
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#define TGPRE (*((uint32_t volatile*)(0x3C7000F0)))
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#define TGCNT (*((uint32_t volatile*)(0x3C7000F4)))
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#define THCON (*((uint32_t volatile*)(0x3C700100)))
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#define THCMD (*((uint32_t volatile*)(0x3C700104)))
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#define THDATA0 (*((uint32_t volatile*)(0x3C700108)))
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#define THDATA1 (*((uint32_t volatile*)(0x3C70010C)))
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#define THPRE (*((uint32_t volatile*)(0x3C700110)))
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#define THCNT (*((uint32_t volatile*)(0x3C700114)))
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2014-11-10 01:39:16 +00:00
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#define TSTAT (*((uint32_t volatile*)(0x3C700118)))
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2011-11-06 22:44:25 +00:00
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#define USEC_TIMER TECNT
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/////USB/////
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#define OTGBASE 0x38400000
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#define PHYBASE 0x3C400000
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2016-07-31 01:40:32 +00:00
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/* OTG PHY control registers */
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#define OPHYPWR (*((uint32_t volatile*)(PHYBASE + 0x000)))
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#define OPHYCLK (*((uint32_t volatile*)(PHYBASE + 0x004)))
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#define ORSTCON (*((uint32_t volatile*)(PHYBASE + 0x008)))
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#define OPHYUNK3 (*((uint32_t volatile*)(PHYBASE + 0x018)))
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#define OPHYUNK1 (*((uint32_t volatile*)(PHYBASE + 0x01c)))
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#define OPHYUNK2 (*((uint32_t volatile*)(PHYBASE + 0x044)))
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/* 9 available EPs (0b00000001111101010000000111101011), 6 used */
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#define USB_NUM_ENDPOINTS 6
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/* Define this if the DWC implemented on this SoC does not support
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DMA or you want to disable it. */
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// #define USB_DW_ARCH_SLAVE
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2011-11-06 22:44:25 +00:00
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/////I2C/////
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2015-09-25 23:35:15 +00:00
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#define I2CCLKGATE(i) ((i) == 1 ? CLOCKGATE_I2C1 : \
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CLOCKGATE_I2C0)
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2016-08-12 12:03:54 +00:00
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/* s5l8702 I2C controller is similar to s5l8700, known differences are:
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* IICCON[5] is not used in s5l8702.
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* IICCON[13:8] are used to enable interrupts.
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IICSTA2[13:8] are used to read the status and write-clear interrupts.
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Known interrupts:
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[13] STOP on bus (TBC)
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[12] START on bus (TBC)
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[8] byte transmited or received in Master mode (not tested in Slave)
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* IICCON[4] does not clear interrupts, it is enabled when a byte is
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transmited or received, in Master mode the tx/rx of the next byte
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starts when it is written as "1".
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*/
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2015-12-17 01:37:18 +00:00
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#define IICCON(bus) (*((uint32_t volatile*)(0x3C600000 + 0x300000 * (bus))))
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#define IICSTAT(bus) (*((uint32_t volatile*)(0x3C600004 + 0x300000 * (bus))))
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#define IICADD(bus) (*((uint32_t volatile*)(0x3C600008 + 0x300000 * (bus))))
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#define IICDS(bus) (*((uint32_t volatile*)(0x3C60000C + 0x300000 * (bus))))
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#define IICUNK10(bus) (*((uint32_t volatile*)(0x3C600010 + 0x300000 * (bus))))
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#define IICUNK14(bus) (*((uint32_t volatile*)(0x3C600014 + 0x300000 * (bus))))
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#define IICUNK18(bus) (*((uint32_t volatile*)(0x3C600018 + 0x300000 * (bus))))
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2016-08-12 12:03:54 +00:00
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#define IICSTA2(bus) (*((uint32_t volatile*)(0x3C600020 + 0x300000 * (bus))))
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2011-11-06 22:44:25 +00:00
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/////INTERRUPT CONTROLLERS/////
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#define VICIRQSTATUS(v) (*((uint32_t volatile*)(0x38E00000 + 0x1000 * (v))))
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#define VICFIQSTATUS(v) (*((uint32_t volatile*)(0x38E00004 + 0x1000 * (v))))
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#define VICRAWINTR(v) (*((uint32_t volatile*)(0x38E00008 + 0x1000 * (v))))
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#define VICINTSELECT(v) (*((uint32_t volatile*)(0x38E0000C + 0x1000 * (v))))
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#define VICINTENABLE(v) (*((uint32_t volatile*)(0x38E00010 + 0x1000 * (v))))
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#define VICINTENCLEAR(v) (*((uint32_t volatile*)(0x38E00014 + 0x1000 * (v))))
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#define VICSOFTINT(v) (*((uint32_t volatile*)(0x38E00018 + 0x1000 * (v))))
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#define VICSOFTINTCLEAR(v) (*((uint32_t volatile*)(0x38E0001C + 0x1000 * (v))))
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#define VICPROTECTION(v) (*((uint32_t volatile*)(0x38E00020 + 0x1000 * (v))))
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#define VICSWPRIORITYMASK(v) (*((uint32_t volatile*)(0x38E00024 + 0x1000 * (v))))
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#define VICPRIORITYDAISY(v) (*((uint32_t volatile*)(0x38E00028 + 0x1000 * (v))))
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#define VICVECTADDR(v, i) (*((uint32_t volatile*)(0x38E00100 + 0x1000 * (v) + 4 * (i))))
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#define VICVECTPRIORITY(v, i) (*((uint32_t volatile*)(0x38E00200 + 0x1000 * (v) + 4 * (i))))
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#define VICADDRESS(v) (*((const void* volatile*)(0x38E00F00 + 0x1000 * (v))))
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#define VIC0IRQSTATUS (*((uint32_t volatile*)(0x38E00000)))
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#define VIC0FIQSTATUS (*((uint32_t volatile*)(0x38E00004)))
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#define VIC0RAWINTR (*((uint32_t volatile*)(0x38E00008)))
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#define VIC0INTSELECT (*((uint32_t volatile*)(0x38E0000C)))
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#define VIC0INTENABLE (*((uint32_t volatile*)(0x38E00010)))
|
|
|
|
|
#define VIC0INTENCLEAR (*((uint32_t volatile*)(0x38E00014)))
|
|
|
|
|
#define VIC0SOFTINT (*((uint32_t volatile*)(0x38E00018)))
|
|
|
|
|
#define VIC0SOFTINTCLEAR (*((uint32_t volatile*)(0x38E0001C)))
|
|
|
|
|
#define VIC0PROTECTION (*((uint32_t volatile*)(0x38E00020)))
|
|
|
|
|
#define VIC0SWPRIORITYMASK (*((uint32_t volatile*)(0x38E00024)))
|
|
|
|
|
#define VIC0PRIORITYDAISY (*((uint32_t volatile*)(0x38E00028)))
|
|
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|
|
#define VIC0VECTADDR(i) (*((const void* volatile*)(0x38E00100 + 4 * (i))))
|
|
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|
|
#define VIC0VECTADDR0 (*((const void* volatile*)(0x38E00100)))
|
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|
|
#define VIC0VECTADDR1 (*((const void* volatile*)(0x38E00104)))
|
|
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|
|
#define VIC0VECTADDR2 (*((const void* volatile*)(0x38E00108)))
|
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|
|
#define VIC0VECTADDR3 (*((const void* volatile*)(0x38E0010C)))
|
|
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|
|
#define VIC0VECTADDR4 (*((const void* volatile*)(0x38E00110)))
|
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|
|
#define VIC0VECTADDR5 (*((const void* volatile*)(0x38E00114)))
|
|
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|
|
#define VIC0VECTADDR6 (*((const void* volatile*)(0x38E00118)))
|
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|
|
#define VIC0VECTADDR7 (*((const void* volatile*)(0x38E0011C)))
|
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|
|
#define VIC0VECTADDR8 (*((const void* volatile*)(0x38E00120)))
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|
|
#define VIC0VECTADDR9 (*((const void* volatile*)(0x38E00124)))
|
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|
#define VIC0VECTADDR10 (*((const void* volatile*)(0x38E00128)))
|
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|
#define VIC0VECTADDR11 (*((const void* volatile*)(0x38E0012C)))
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|
|
#define VIC0VECTADDR12 (*((const void* volatile*)(0x38E00130)))
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|
|
#define VIC0VECTADDR13 (*((const void* volatile*)(0x38E00134)))
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|
|
#define VIC0VECTADDR14 (*((const void* volatile*)(0x38E00138)))
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|
|
#define VIC0VECTADDR15 (*((const void* volatile*)(0x38E0013C)))
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|
|
#define VIC0VECTADDR16 (*((const void* volatile*)(0x38E00140)))
|
|
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|
|
#define VIC0VECTADDR17 (*((const void* volatile*)(0x38E00144)))
|
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|
|
#define VIC0VECTADDR18 (*((const void* volatile*)(0x38E00148)))
|
|
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|
|
#define VIC0VECTADDR19 (*((const void* volatile*)(0x38E0014C)))
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|
|
#define VIC0VECTADDR20 (*((const void* volatile*)(0x38E00150)))
|
|
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|
|
#define VIC0VECTADDR21 (*((const void* volatile*)(0x38E00154)))
|
|
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|
|
#define VIC0VECTADDR22 (*((const void* volatile*)(0x38E00158)))
|
|
|
|
|
#define VIC0VECTADDR23 (*((const void* volatile*)(0x38E0015C)))
|
|
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|
|
#define VIC0VECTADDR24 (*((const void* volatile*)(0x38E00160)))
|
|
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|
|
#define VIC0VECTADDR25 (*((const void* volatile*)(0x38E00164)))
|
|
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|
|
#define VIC0VECTADDR26 (*((const void* volatile*)(0x38E00168)))
|
|
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|
|
#define VIC0VECTADDR27 (*((const void* volatile*)(0x38E0016C)))
|
|
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|
|
#define VIC0VECTADDR28 (*((const void* volatile*)(0x38E00170)))
|
|
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|
|
#define VIC0VECTADDR29 (*((const void* volatile*)(0x38E00174)))
|
|
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|
|
#define VIC0VECTADDR30 (*((const void* volatile*)(0x38E00178)))
|
|
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|
|
#define VIC0VECTADDR31 (*((const void* volatile*)(0x38E0017C)))
|
|
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|
|
#define VIC0VECTPRIORITY(i) (*((uint32_t volatile*)(0x38E00200 + 4 * (i))))
|
|
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|
|
#define VIC0VECTPRIORITY0 (*((uint32_t volatile*)(0x38E00200)))
|
|
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|
|
#define VIC0VECTPRIORITY1 (*((uint32_t volatile*)(0x38E00204)))
|
|
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|
|
#define VIC0VECTPRIORITY2 (*((uint32_t volatile*)(0x38E00208)))
|
|
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|
|
#define VIC0VECTPRIORITY3 (*((uint32_t volatile*)(0x38E0020C)))
|
|
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|
|
#define VIC0VECTPRIORITY4 (*((uint32_t volatile*)(0x38E00210)))
|
|
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|
|
#define VIC0VECTPRIORITY5 (*((uint32_t volatile*)(0x38E00214)))
|
|
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|
|
#define VIC0VECTPRIORITY6 (*((uint32_t volatile*)(0x38E00218)))
|
|
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|
|
#define VIC0VECTPRIORITY7 (*((uint32_t volatile*)(0x38E0021C)))
|
|
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|
|
#define VIC0VECTPRIORITY8 (*((uint32_t volatile*)(0x38E00220)))
|
|
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|
|
#define VIC0VECTPRIORITY9 (*((uint32_t volatile*)(0x38E00224)))
|
|
|
|
|
#define VIC0VECTPRIORITY10 (*((uint32_t volatile*)(0x38E00228)))
|
|
|
|
|
#define VIC0VECTPRIORITY11 (*((uint32_t volatile*)(0x38E0022C)))
|
|
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|
|
#define VIC0VECTPRIORITY12 (*((uint32_t volatile*)(0x38E00230)))
|
|
|
|
|
#define VIC0VECTPRIORITY13 (*((uint32_t volatile*)(0x38E00234)))
|
|
|
|
|
#define VIC0VECTPRIORITY14 (*((uint32_t volatile*)(0x38E00238)))
|
|
|
|
|
#define VIC0VECTPRIORITY15 (*((uint32_t volatile*)(0x38E0023C)))
|
|
|
|
|
#define VIC0VECTPRIORITY16 (*((uint32_t volatile*)(0x38E00240)))
|
|
|
|
|
#define VIC0VECTPRIORITY17 (*((uint32_t volatile*)(0x38E00244)))
|
|
|
|
|
#define VIC0VECTPRIORITY18 (*((uint32_t volatile*)(0x38E00248)))
|
|
|
|
|
#define VIC0VECTPRIORITY19 (*((uint32_t volatile*)(0x38E0024C)))
|
|
|
|
|
#define VIC0VECTPRIORITY20 (*((uint32_t volatile*)(0x38E00250)))
|
|
|
|
|
#define VIC0VECTPRIORITY21 (*((uint32_t volatile*)(0x38E00254)))
|
|
|
|
|
#define VIC0VECTPRIORITY22 (*((uint32_t volatile*)(0x38E00258)))
|
|
|
|
|
#define VIC0VECTPRIORITY23 (*((uint32_t volatile*)(0x38E0025C)))
|
|
|
|
|
#define VIC0VECTPRIORITY24 (*((uint32_t volatile*)(0x38E00260)))
|
|
|
|
|
#define VIC0VECTPRIORITY25 (*((uint32_t volatile*)(0x38E00264)))
|
|
|
|
|
#define VIC0VECTPRIORITY26 (*((uint32_t volatile*)(0x38E00268)))
|
|
|
|
|
#define VIC0VECTPRIORITY27 (*((uint32_t volatile*)(0x38E0026C)))
|
|
|
|
|
#define VIC0VECTPRIORITY28 (*((uint32_t volatile*)(0x38E00270)))
|
|
|
|
|
#define VIC0VECTPRIORITY29 (*((uint32_t volatile*)(0x38E00274)))
|
|
|
|
|
#define VIC0VECTPRIORITY30 (*((uint32_t volatile*)(0x38E00278)))
|
|
|
|
|
#define VIC0VECTPRIORITY31 (*((uint32_t volatile*)(0x38E0027C)))
|
|
|
|
|
#define VIC0ADDRESS (*((void* volatile*)(0x38E00F00)))
|
|
|
|
|
#define VIC1IRQSTATUS (*((uint32_t volatile*)(0x38E01000)))
|
|
|
|
|
#define VIC1FIQSTATUS (*((uint32_t volatile*)(0x38E01004)))
|
|
|
|
|
#define VIC1RAWINTR (*((uint32_t volatile*)(0x38E01008)))
|
|
|
|
|
#define VIC1INTSELECT (*((uint32_t volatile*)(0x38E0100C)))
|
|
|
|
|
#define VIC1INTENABLE (*((uint32_t volatile*)(0x38E01010)))
|
|
|
|
|
#define VIC1INTENCLEAR (*((uint32_t volatile*)(0x38E01014)))
|
|
|
|
|
#define VIC1SOFTINT (*((uint32_t volatile*)(0x38E01018)))
|
|
|
|
|
#define VIC1SOFTINTCLEAR (*((uint32_t volatile*)(0x38E0101C)))
|
|
|
|
|
#define VIC1PROTECTION (*((uint32_t volatile*)(0x38E01020)))
|
|
|
|
|
#define VIC1SWPRIORITYMASK (*((uint32_t volatile*)(0x38E01024)))
|
|
|
|
|
#define VIC1PRIORITYDAISY (*((uint32_t volatile*)(0x38E01028)))
|
|
|
|
|
#define VIC1VECTADDR(i) (*((const void* volatile*)(0x38E01100 + 4 * (i))))
|
|
|
|
|
#define VIC1VECTADDR0 (*((const void* volatile*)(0x38E01100)))
|
|
|
|
|
#define VIC1VECTADDR1 (*((const void* volatile*)(0x38E01104)))
|
|
|
|
|
#define VIC1VECTADDR2 (*((const void* volatile*)(0x38E01108)))
|
|
|
|
|
#define VIC1VECTADDR3 (*((const void* volatile*)(0x38E0110C)))
|
|
|
|
|
#define VIC1VECTADDR4 (*((const void* volatile*)(0x38E01110)))
|
|
|
|
|
#define VIC1VECTADDR5 (*((const void* volatile*)(0x38E01114)))
|
|
|
|
|
#define VIC1VECTADDR6 (*((const void* volatile*)(0x38E01118)))
|
|
|
|
|
#define VIC1VECTADDR7 (*((const void* volatile*)(0x38E0111C)))
|
|
|
|
|
#define VIC1VECTADDR8 (*((const void* volatile*)(0x38E01120)))
|
|
|
|
|
#define VIC1VECTADDR9 (*((const void* volatile*)(0x38E01124)))
|
|
|
|
|
#define VIC1VECTADDR10 (*((const void* volatile*)(0x38E01128)))
|
|
|
|
|
#define VIC1VECTADDR11 (*((const void* volatile*)(0x38E0112C)))
|
|
|
|
|
#define VIC1VECTADDR12 (*((const void* volatile*)(0x38E01130)))
|
|
|
|
|
#define VIC1VECTADDR13 (*((const void* volatile*)(0x38E01134)))
|
|
|
|
|
#define VIC1VECTADDR14 (*((const void* volatile*)(0x38E01138)))
|
|
|
|
|
#define VIC1VECTADDR15 (*((const void* volatile*)(0x38E0113C)))
|
|
|
|
|
#define VIC1VECTADDR16 (*((const void* volatile*)(0x38E01140)))
|
|
|
|
|
#define VIC1VECTADDR17 (*((const void* volatile*)(0x38E01144)))
|
|
|
|
|
#define VIC1VECTADDR18 (*((const void* volatile*)(0x38E01148)))
|
|
|
|
|
#define VIC1VECTADDR19 (*((const void* volatile*)(0x38E0114C)))
|
|
|
|
|
#define VIC1VECTADDR20 (*((const void* volatile*)(0x38E01150)))
|
|
|
|
|
#define VIC1VECTADDR21 (*((const void* volatile*)(0x38E01154)))
|
|
|
|
|
#define VIC1VECTADDR22 (*((const void* volatile*)(0x38E01158)))
|
|
|
|
|
#define VIC1VECTADDR23 (*((const void* volatile*)(0x38E0115C)))
|
|
|
|
|
#define VIC1VECTADDR24 (*((const void* volatile*)(0x38E01160)))
|
|
|
|
|
#define VIC1VECTADDR25 (*((const void* volatile*)(0x38E01164)))
|
|
|
|
|
#define VIC1VECTADDR26 (*((const void* volatile*)(0x38E01168)))
|
|
|
|
|
#define VIC1VECTADDR27 (*((const void* volatile*)(0x38E0116C)))
|
|
|
|
|
#define VIC1VECTADDR28 (*((const void* volatile*)(0x38E01170)))
|
|
|
|
|
#define VIC1VECTADDR29 (*((const void* volatile*)(0x38E01174)))
|
|
|
|
|
#define VIC1VECTADDR30 (*((const void* volatile*)(0x38E01178)))
|
|
|
|
|
#define VIC1VECTADDR31 (*((const void* volatile*)(0x38E0117C)))
|
|
|
|
|
#define VIC1VECTPRIORITY(i) (*((uint32_t volatile*)(0x38E01200 + 4 * (i))))
|
|
|
|
|
#define VIC1VECTPRIORITY0 (*((uint32_t volatile*)(0x38E01200)))
|
|
|
|
|
#define VIC1VECTPRIORITY1 (*((uint32_t volatile*)(0x38E01204)))
|
|
|
|
|
#define VIC1VECTPRIORITY2 (*((uint32_t volatile*)(0x38E01208)))
|
|
|
|
|
#define VIC1VECTPRIORITY3 (*((uint32_t volatile*)(0x38E0120C)))
|
|
|
|
|
#define VIC1VECTPRIORITY4 (*((uint32_t volatile*)(0x38E01210)))
|
|
|
|
|
#define VIC1VECTPRIORITY5 (*((uint32_t volatile*)(0x38E01214)))
|
|
|
|
|
#define VIC1VECTPRIORITY6 (*((uint32_t volatile*)(0x38E01218)))
|
|
|
|
|
#define VIC1VECTPRIORITY7 (*((uint32_t volatile*)(0x38E0121C)))
|
|
|
|
|
#define VIC1VECTPRIORITY8 (*((uint32_t volatile*)(0x38E01220)))
|
|
|
|
|
#define VIC1VECTPRIORITY9 (*((uint32_t volatile*)(0x38E01224)))
|
|
|
|
|
#define VIC1VECTPRIORITY10 (*((uint32_t volatile*)(0x38E01228)))
|
|
|
|
|
#define VIC1VECTPRIORITY11 (*((uint32_t volatile*)(0x38E0122C)))
|
|
|
|
|
#define VIC1VECTPRIORITY12 (*((uint32_t volatile*)(0x38E01230)))
|
|
|
|
|
#define VIC1VECTPRIORITY13 (*((uint32_t volatile*)(0x38E01234)))
|
|
|
|
|
#define VIC1VECTPRIORITY14 (*((uint32_t volatile*)(0x38E01238)))
|
|
|
|
|
#define VIC1VECTPRIORITY15 (*((uint32_t volatile*)(0x38E0123C)))
|
|
|
|
|
#define VIC1VECTPRIORITY16 (*((uint32_t volatile*)(0x38E01240)))
|
|
|
|
|
#define VIC1VECTPRIORITY17 (*((uint32_t volatile*)(0x38E01244)))
|
|
|
|
|
#define VIC1VECTPRIORITY18 (*((uint32_t volatile*)(0x38E01248)))
|
|
|
|
|
#define VIC1VECTPRIORITY19 (*((uint32_t volatile*)(0x38E0124C)))
|
|
|
|
|
#define VIC1VECTPRIORITY20 (*((uint32_t volatile*)(0x38E01250)))
|
|
|
|
|
#define VIC1VECTPRIORITY21 (*((uint32_t volatile*)(0x38E01254)))
|
|
|
|
|
#define VIC1VECTPRIORITY22 (*((uint32_t volatile*)(0x38E01258)))
|
|
|
|
|
#define VIC1VECTPRIORITY23 (*((uint32_t volatile*)(0x38E0125C)))
|
|
|
|
|
#define VIC1VECTPRIORITY24 (*((uint32_t volatile*)(0x38E01260)))
|
|
|
|
|
#define VIC1VECTPRIORITY25 (*((uint32_t volatile*)(0x38E01264)))
|
|
|
|
|
#define VIC1VECTPRIORITY26 (*((uint32_t volatile*)(0x38E01268)))
|
|
|
|
|
#define VIC1VECTPRIORITY27 (*((uint32_t volatile*)(0x38E0126C)))
|
|
|
|
|
#define VIC1VECTPRIORITY28 (*((uint32_t volatile*)(0x38E01270)))
|
|
|
|
|
#define VIC1VECTPRIORITY29 (*((uint32_t volatile*)(0x38E01274)))
|
|
|
|
|
#define VIC1VECTPRIORITY30 (*((uint32_t volatile*)(0x38E01278)))
|
|
|
|
|
#define VIC1VECTPRIORITY31 (*((uint32_t volatile*)(0x38E0127C)))
|
|
|
|
|
#define VIC1ADDRESS (*((void* volatile*)(0x38E01F00)))
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/////GPIO/////
|
|
|
|
|
#define PCON(i) (*((uint32_t volatile*)(0x3cf00000 + ((i) << 5))))
|
|
|
|
|
#define PDAT(i) (*((uint32_t volatile*)(0x3cf00004 + ((i) << 5))))
|
|
|
|
|
#define PUNA(i) (*((uint32_t volatile*)(0x3cf00008 + ((i) << 5))))
|
|
|
|
|
#define PUNB(i) (*((uint32_t volatile*)(0x3cf0000c + ((i) << 5))))
|
2015-12-17 01:37:18 +00:00
|
|
|
#define PUNC(i) (*((uint32_t volatile*)(0x3cf00010 + ((i) << 5))))
|
2011-11-06 22:44:25 +00:00
|
|
|
#define PCON0 (*((uint32_t volatile*)(0x3cf00000)))
|
|
|
|
|
#define PDAT0 (*((uint32_t volatile*)(0x3cf00004)))
|
|
|
|
|
#define PCON1 (*((uint32_t volatile*)(0x3cf00020)))
|
|
|
|
|
#define PDAT1 (*((uint32_t volatile*)(0x3cf00024)))
|
|
|
|
|
#define PCON2 (*((uint32_t volatile*)(0x3cf00040)))
|
|
|
|
|
#define PDAT2 (*((uint32_t volatile*)(0x3cf00044)))
|
|
|
|
|
#define PCON3 (*((uint32_t volatile*)(0x3cf00060)))
|
|
|
|
|
#define PDAT3 (*((uint32_t volatile*)(0x3cf00064)))
|
|
|
|
|
#define PCON4 (*((uint32_t volatile*)(0x3cf00080)))
|
|
|
|
|
#define PDAT4 (*((uint32_t volatile*)(0x3cf00084)))
|
|
|
|
|
#define PCON5 (*((uint32_t volatile*)(0x3cf000a0)))
|
|
|
|
|
#define PDAT5 (*((uint32_t volatile*)(0x3cf000a4)))
|
|
|
|
|
#define PCON6 (*((uint32_t volatile*)(0x3cf000c0)))
|
|
|
|
|
#define PDAT6 (*((uint32_t volatile*)(0x3cf000c4)))
|
|
|
|
|
#define PCON7 (*((uint32_t volatile*)(0x3cf000e0)))
|
|
|
|
|
#define PDAT7 (*((uint32_t volatile*)(0x3cf000e4)))
|
|
|
|
|
#define PCON8 (*((uint32_t volatile*)(0x3cf00100)))
|
|
|
|
|
#define PDAT8 (*((uint32_t volatile*)(0x3cf00104)))
|
|
|
|
|
#define PCON9 (*((uint32_t volatile*)(0x3cf00120)))
|
|
|
|
|
#define PDAT9 (*((uint32_t volatile*)(0x3cf00124)))
|
|
|
|
|
#define PCONA (*((uint32_t volatile*)(0x3cf00140)))
|
|
|
|
|
#define PDATA (*((uint32_t volatile*)(0x3cf00144)))
|
|
|
|
|
#define PCONB (*((uint32_t volatile*)(0x3cf00160)))
|
|
|
|
|
#define PDATB (*((uint32_t volatile*)(0x3cf00164)))
|
|
|
|
|
#define PCONC (*((uint32_t volatile*)(0x3cf00180)))
|
|
|
|
|
#define PDATC (*((uint32_t volatile*)(0x3cf00184)))
|
|
|
|
|
#define PCOND (*((uint32_t volatile*)(0x3cf001a0)))
|
|
|
|
|
#define PDATD (*((uint32_t volatile*)(0x3cf001a4)))
|
|
|
|
|
#define PCONE (*((uint32_t volatile*)(0x3cf001c0)))
|
|
|
|
|
#define PDATE (*((uint32_t volatile*)(0x3cf001c4)))
|
|
|
|
|
#define PCONF (*((uint32_t volatile*)(0x3cf001e0)))
|
|
|
|
|
#define PDATF (*((uint32_t volatile*)(0x3cf001e4)))
|
|
|
|
|
#define GPIOCMD (*((uint32_t volatile*)(0x3cf00200)))
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/////SPI/////
|
|
|
|
|
#define SPIBASE(i) ((i) == 2 ? 0x3d200000 : \
|
|
|
|
|
(i) == 1 ? 0x3ce00000 : \
|
|
|
|
|
0x3c300000)
|
2015-09-25 23:35:15 +00:00
|
|
|
#define SPICLKGATE(i) ((i) == 2 ? CLOCKGATE_SPI2 : \
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|
(i) == 1 ? CLOCKGATE_SPI1 : \
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|
CLOCKGATE_SPI0)
|
2011-11-06 22:44:25 +00:00
|
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|
#define SPIDMA(i) ((i) == 2 ? 0xd : \
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|
(i) == 1 ? 0xf : \
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|
0x5)
|
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|
#define SPICTRL(i) (*((uint32_t volatile*)(SPIBASE(i))))
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|
#define SPISETUP(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x4)))
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#define SPISTATUS(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x8)))
|
2015-12-17 01:37:18 +00:00
|
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|
#define SPIPIN(i) (*((uint32_t volatile*)(SPIBASE(i) + 0xc)))
|
2011-11-06 22:44:25 +00:00
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|
#define SPITXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x10)))
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#define SPIRXDATA(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x20)))
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#define SPICLKDIV(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x30)))
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|
#define SPIRXLIMIT(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x34)))
|
2015-12-17 01:37:18 +00:00
|
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|
#define SPIDD(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x38))) /* TBC */
|
2011-11-06 22:44:25 +00:00
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|
/////AES/////
|
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|
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|
#define AESCONTROL (*((uint32_t volatile*)(0x38c00000)))
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|
|
#define AESGO (*((uint32_t volatile*)(0x38c00004)))
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|
|
#define AESUNKREG0 (*((uint32_t volatile*)(0x38c00008)))
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|
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|
#define AESSTATUS (*((uint32_t volatile*)(0x38c0000c)))
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|
#define AESUNKREG1 (*((uint32_t volatile*)(0x38c00010)))
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|
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|
#define AESKEYLEN (*((uint32_t volatile*)(0x38c00014)))
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|
#define AESOUTSIZE (*((uint32_t volatile*)(0x38c00018)))
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|
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|
#define AESOUTADDR (*((void* volatile*)(0x38c00020)))
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|
|
|
#define AESINSIZE (*((uint32_t volatile*)(0x38c00024)))
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|
|
|
#define AESINADDR (*((const void* volatile*)(0x38c00028)))
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|
|
|
#define AESAUXSIZE (*((uint32_t volatile*)(0x38c0002c)))
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|
|
|
#define AESAUXADDR (*((void* volatile*)(0x38c00030)))
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|
|
|
#define AESSIZE3 (*((uint32_t volatile*)(0x38c00034)))
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|
|
|
#define AESKEY ((uint32_t volatile*)(0x38c0004c))
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|
|
|
#define AESTYPE (*((uint32_t volatile*)(0x38c0006c)))
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|
|
|
#define AESIV ((uint32_t volatile*)(0x38c00074))
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|
|
|
#define AESTYPE2 (*((uint32_t volatile*)(0x38c00088)))
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|
|
|
#define AESUNKREG2 (*((uint32_t volatile*)(0x38c0008c)))
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|
|
|
|
/////SHA1/////
|
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|
|
#define SHA1CONFIG (*((uint32_t volatile*)(0x38000000)))
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|
|
|
|
#define SHA1RESET (*((uint32_t volatile*)(0x38000004)))
|
|
|
|
|
#define SHA1RESULT ((uint32_t volatile*)(0x38000020))
|
|
|
|
|
#define SHA1DATAIN ((uint32_t volatile*)(0x38000040))
|
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|
|
|
/////LCD/////
|
|
|
|
|
#define LCD_BASE (0x38300000)
|
|
|
|
|
#define LCD_CONFIG (*((uint32_t volatile*)(0x38300000)))
|
|
|
|
|
#define LCD_WCMD (*((uint32_t volatile*)(0x38300004)))
|
|
|
|
|
#define LCD_STATUS (*((uint32_t volatile*)(0x3830001c)))
|
2015-09-26 04:06:42 +00:00
|
|
|
#define LCD_PHTIME (*((uint32_t volatile*)(0x38300020)))
|
2011-11-06 22:44:25 +00:00
|
|
|
#define LCD_WDATA (*((uint32_t volatile*)(0x38300040)))
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
/////ATA/////
|
|
|
|
|
#define ATA_CONTROL (*((uint32_t volatile*)(0x38700000)))
|
|
|
|
|
#define ATA_STATUS (*((uint32_t volatile*)(0x38700004)))
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|
|
|
#define ATA_COMMAND (*((uint32_t volatile*)(0x38700008)))
|
|
|
|
|
#define ATA_SWRST (*((uint32_t volatile*)(0x3870000c)))
|
|
|
|
|
#define ATA_IRQ (*((uint32_t volatile*)(0x38700010)))
|
|
|
|
|
#define ATA_IRQ_MASK (*((uint32_t volatile*)(0x38700014)))
|
|
|
|
|
#define ATA_CFG (*((uint32_t volatile*)(0x38700018)))
|
|
|
|
|
#define ATA_MDMA_TIME (*((uint32_t volatile*)(0x38700028)))
|
|
|
|
|
#define ATA_PIO_TIME (*((uint32_t volatile*)(0x3870002c)))
|
|
|
|
|
#define ATA_UDMA_TIME (*((uint32_t volatile*)(0x38700030)))
|
|
|
|
|
#define ATA_XFR_NUM (*((uint32_t volatile*)(0x38700034)))
|
|
|
|
|
#define ATA_XFR_CNT (*((uint32_t volatile*)(0x38700038)))
|
|
|
|
|
#define ATA_TBUF_START (*((void* volatile*)(0x3870003c)))
|
|
|
|
|
#define ATA_TBUF_SIZE (*((uint32_t volatile*)(0x38700040)))
|
|
|
|
|
#define ATA_SBUF_START (*((void* volatile*)(0x38700044)))
|
|
|
|
|
#define ATA_SBUF_SIZE (*((uint32_t volatile*)(0x38700048)))
|
|
|
|
|
#define ATA_CADR_TBUF (*((void* volatile*)(0x3870004c)))
|
|
|
|
|
#define ATA_CADR_SBUF (*((void* volatile*)(0x38700050)))
|
|
|
|
|
#define ATA_PIO_DTR (*((uint32_t volatile*)(0x38700054)))
|
|
|
|
|
#define ATA_PIO_FED (*((uint32_t volatile*)(0x38700058)))
|
|
|
|
|
#define ATA_PIO_SCR (*((uint32_t volatile*)(0x3870005c)))
|
|
|
|
|
#define ATA_PIO_LLR (*((uint32_t volatile*)(0x38700060)))
|
|
|
|
|
#define ATA_PIO_LMR (*((uint32_t volatile*)(0x38700064)))
|
|
|
|
|
#define ATA_PIO_LHR (*((uint32_t volatile*)(0x38700068)))
|
|
|
|
|
#define ATA_PIO_DVR (*((uint32_t volatile*)(0x3870006c)))
|
|
|
|
|
#define ATA_PIO_CSD (*((uint32_t volatile*)(0x38700070)))
|
|
|
|
|
#define ATA_PIO_DAD (*((uint32_t volatile*)(0x38700074)))
|
|
|
|
|
#define ATA_PIO_READY (*((uint32_t volatile*)(0x38700078)))
|
|
|
|
|
#define ATA_PIO_RDATA (*((uint32_t volatile*)(0x3870007c)))
|
|
|
|
|
#define ATA_BUS_FIFO_STATUS (*((uint32_t volatile*)(0x38700080)))
|
|
|
|
|
#define ATA_FIFO_STATUS (*((uint32_t volatile*)(0x38700084)))
|
|
|
|
|
#define ATA_DMA_ADDR (*((void* volatile*)(0x38700088)))
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/////SDCI/////
|
|
|
|
|
#define SDCI_CTRL (*((uint32_t volatile*)(0x38b00000)))
|
|
|
|
|
#define SDCI_DCTRL (*((uint32_t volatile*)(0x38b00004)))
|
|
|
|
|
#define SDCI_CMD (*((uint32_t volatile*)(0x38b00008)))
|
|
|
|
|
#define SDCI_ARGU (*((uint32_t volatile*)(0x38b0000c)))
|
|
|
|
|
#define SDCI_STATE (*((uint32_t volatile*)(0x38b00010)))
|
|
|
|
|
#define SDCI_STAC (*((uint32_t volatile*)(0x38b00014)))
|
|
|
|
|
#define SDCI_DSTA (*((uint32_t volatile*)(0x38b00018)))
|
|
|
|
|
#define SDCI_FSTA (*((uint32_t volatile*)(0x38b0001c)))
|
|
|
|
|
#define SDCI_RESP0 (*((uint32_t volatile*)(0x38b00020)))
|
|
|
|
|
#define SDCI_RESP1 (*((uint32_t volatile*)(0x38b00024)))
|
|
|
|
|
#define SDCI_RESP2 (*((uint32_t volatile*)(0x38b00028)))
|
|
|
|
|
#define SDCI_RESP3 (*((uint32_t volatile*)(0x38b0002c)))
|
|
|
|
|
#define SDCI_CDIV (*((uint32_t volatile*)(0x38b00030)))
|
|
|
|
|
#define SDCI_SDIO_CSR (*((uint32_t volatile*)(0x38b00034)))
|
|
|
|
|
#define SDCI_IRQ (*((uint32_t volatile*)(0x38b00038)))
|
|
|
|
|
#define SDCI_IRQ_MASK (*((uint32_t volatile*)(0x38b0003c)))
|
|
|
|
|
#define SDCI_DATA (*((uint32_t volatile*)(0x38b00040)))
|
|
|
|
|
#define SDCI_DMAADDR (*((void* volatile*)(0x38b00044)))
|
|
|
|
|
#define SDCI_DMASIZE (*((uint32_t volatile*)(0x38b00048)))
|
|
|
|
|
#define SDCI_DMACOUNT (*((uint32_t volatile*)(0x38b0004c)))
|
|
|
|
|
#define SDCI_RESET (*((uint32_t volatile*)(0x38b0006c)))
|
|
|
|
|
|
|
|
|
|
#define SDCI_CTRL_SDCIEN BIT(0)
|
|
|
|
|
#define SDCI_CTRL_CARD_TYPE_MASK BIT(1)
|
|
|
|
|
#define SDCI_CTRL_CARD_TYPE_SD 0
|
|
|
|
|
#define SDCI_CTRL_CARD_TYPE_MMC BIT(1)
|
|
|
|
|
#define SDCI_CTRL_BUS_WIDTH_MASK BITRANGE(2, 3)
|
|
|
|
|
#define SDCI_CTRL_BUS_WIDTH_1BIT 0
|
|
|
|
|
#define SDCI_CTRL_BUS_WIDTH_4BIT BIT(2)
|
|
|
|
|
#define SDCI_CTRL_BUS_WIDTH_8BIT BIT(3)
|
|
|
|
|
#define SDCI_CTRL_DMA_EN BIT(4)
|
|
|
|
|
#define SDCI_CTRL_L_ENDIAN BIT(5)
|
|
|
|
|
#define SDCI_CTRL_DMA_REQ_CON_MASK BIT(6)
|
|
|
|
|
#define SDCI_CTRL_DMA_REQ_CON_NEMPTY 0
|
|
|
|
|
#define SDCI_CTRL_DMA_REQ_CON_FULL BIT(6)
|
|
|
|
|
#define SDCI_CTRL_CLK_SEL_MASK BIT(7)
|
|
|
|
|
#define SDCI_CTRL_CLK_SEL_PCLK 0
|
|
|
|
|
#define SDCI_CTRL_CLK_SEL_SDCLK BIT(7)
|
|
|
|
|
#define SDCI_CTRL_BIT_8 BIT(8)
|
|
|
|
|
#define SDCI_CTRL_BIT_14 BIT(14)
|
|
|
|
|
|
|
|
|
|
#define SDCI_DCTRL_TXFIFORST BIT(0)
|
|
|
|
|
#define SDCI_DCTRL_RXFIFORST BIT(1)
|
|
|
|
|
#define SDCI_DCTRL_TRCONT_MASK BITRANGE(4, 5)
|
|
|
|
|
#define SDCI_DCTRL_TRCONT_TX BIT(4)
|
|
|
|
|
#define SDCI_DCTRL_BUS_TEST_MASK BITRANGE(6, 7)
|
|
|
|
|
#define SDCI_DCTRL_BUS_TEST_TX BIT(6)
|
|
|
|
|
#define SDCI_DCTRL_BUS_TEST_RX BIT(7)
|
|
|
|
|
|
|
|
|
|
#define SDCI_CDIV_CLKDIV_MASK BITRANGE(0, 7)
|
|
|
|
|
#define SDCI_CDIV_CLKDIV(x) ((x) >> 1)
|
|
|
|
|
#define SDCI_CDIV_CLKDIV_2 BIT(0)
|
|
|
|
|
#define SDCI_CDIV_CLKDIV_4 BIT(1)
|
|
|
|
|
#define SDCI_CDIV_CLKDIV_8 BIT(2)
|
|
|
|
|
#define SDCI_CDIV_CLKDIV_16 BIT(3)
|
|
|
|
|
#define SDCI_CDIV_CLKDIV_32 BIT(4)
|
|
|
|
|
#define SDCI_CDIV_CLKDIV_64 BIT(5)
|
|
|
|
|
#define SDCI_CDIV_CLKDIV_128 BIT(6)
|
|
|
|
|
#define SDCI_CDIV_CLKDIV_256 BIT(7)
|
|
|
|
|
|
|
|
|
|
#define SDCI_CMD_CMD_NUM_MASK BITRANGE(0, 5)
|
|
|
|
|
#define SDCI_CMD_CMD_NUM_SHIFT 0
|
|
|
|
|
#define SDCI_CMD_CMD_NUM(x) (x)
|
|
|
|
|
#define SDCI_CMD_CMD_TYPE_MASK BITRANGE(6, 7)
|
|
|
|
|
#define SDCI_CMD_CMD_TYPE_BC 0
|
|
|
|
|
#define SDCI_CMD_CMD_TYPE_BCR BIT(6)
|
|
|
|
|
#define SDCI_CMD_CMD_TYPE_AC BIT(7)
|
|
|
|
|
#define SDCI_CMD_CMD_TYPE_ADTC (BIT(6) | BIT(7))
|
|
|
|
|
#define SDCI_CMD_CMD_RD_WR BIT(8)
|
|
|
|
|
#define SDCI_CMD_RES_TYPE_MASK BITRANGE(16, 18)
|
|
|
|
|
#define SDCI_CMD_RES_TYPE_NONE 0
|
|
|
|
|
#define SDCI_CMD_RES_TYPE_R1 BIT(16)
|
|
|
|
|
#define SDCI_CMD_RES_TYPE_R2 BIT(17)
|
|
|
|
|
#define SDCI_CMD_RES_TYPE_R3 (BIT(16) | BIT(17))
|
|
|
|
|
#define SDCI_CMD_RES_TYPE_R4 BIT(18)
|
|
|
|
|
#define SDCI_CMD_RES_TYPE_R5 (BIT(16) | BIT(18))
|
|
|
|
|
#define SDCI_CMD_RES_TYPE_R6 (BIT(17) | BIT(18))
|
|
|
|
|
#define SDCI_CMD_RES_BUSY BIT(19)
|
|
|
|
|
#define SDCI_CMD_RES_SIZE_MASK BIT(20)
|
|
|
|
|
#define SDCI_CMD_RES_SIZE_48 0
|
|
|
|
|
#define SDCI_CMD_RES_SIZE_136 BIT(20)
|
|
|
|
|
#define SDCI_CMD_NCR_NID_MASK BIT(21)
|
|
|
|
|
#define SDCI_CMD_NCR_NID_NCR 0
|
|
|
|
|
#define SDCI_CMD_NCR_NID_NID BIT(21)
|
|
|
|
|
#define SDCI_CMD_CMDSTR BIT(31)
|
|
|
|
|
|
|
|
|
|
#define SDCI_STATE_DAT_STATE_MASK BITRANGE(0, 3)
|
|
|
|
|
#define SDCI_STATE_DAT_STATE_IDLE 0
|
|
|
|
|
#define SDCI_STATE_DAT_STATE_DAT_RCV BIT(0)
|
|
|
|
|
#define SDCI_STATE_DAT_STATE_CRC_RCV BIT(1)
|
|
|
|
|
#define SDCI_STATE_DAT_STATE_DAT_END (BIT(0) | BIT(1))
|
|
|
|
|
#define SDCI_STATE_DAT_STATE_DAT_SET BIT(2)
|
|
|
|
|
#define SDCI_STATE_DAT_STATE_DAT_OUT (BIT(0) | BIT(2))
|
|
|
|
|
#define SDCI_STATE_DAT_STATE_CRC_TIME (BIT(1) | BIT(2))
|
|
|
|
|
#define SDCI_STATE_DAT_STATE_CRC_OUT (BIT(0) | BIT(1) | BIT(2))
|
|
|
|
|
#define SDCI_STATE_DAT_STATE_ENDB_OUT BIT(3)
|
|
|
|
|
#define SDCI_STATE_DAT_STATE_ENDB_STOD (BIT(0) | BIT(3))
|
|
|
|
|
#define SDCI_STATE_DAT_STATE_DAT_CRCR (BIT(1) | BIT(3))
|
|
|
|
|
#define SDCI_STATE_DAT_STATE_CARD_PRG (BIT(0) | BIT(1) | BIT(3))
|
|
|
|
|
#define SDCI_STATE_DAT_STATE_DAT_BUSY (BIT(2) | BIT(3))
|
|
|
|
|
#define SDCI_STATE_CMD_STATE_MASK (BIT(4) | BIT(5) | BIT(6))
|
|
|
|
|
#define SDCI_STATE_CMD_STATE_CMD_IDLE 0
|
|
|
|
|
#define SDCI_STATE_CMD_STATE_CMD_CMDO BIT(4)
|
|
|
|
|
#define SDCI_STATE_CMD_STATE_CMD_CRCO BIT(5)
|
|
|
|
|
#define SDCI_STATE_CMD_STATE_CMD_TOUT (BIT(4) | BIT(5))
|
|
|
|
|
#define SDCI_STATE_CMD_STATE_CMD_RESR BIT(6)
|
|
|
|
|
#define SDCI_STATE_CMD_STATE_CMD_INTV (BIT(4) | BIT(6))
|
|
|
|
|
|
|
|
|
|
#define SDCI_STAC_CLR_CMDEND BIT(2)
|
|
|
|
|
#define SDCI_STAC_CLR_BIT_3 BIT(3)
|
|
|
|
|
#define SDCI_STAC_CLR_RESEND BIT(4)
|
|
|
|
|
#define SDCI_STAC_CLR_DATEND BIT(6)
|
|
|
|
|
#define SDCI_STAC_CLR_DAT_CRCEND BIT(7)
|
|
|
|
|
#define SDCI_STAC_CLR_CRC_STAEND BIT(8)
|
|
|
|
|
#define SDCI_STAC_CLR_RESTOUTE BIT(15)
|
|
|
|
|
#define SDCI_STAC_CLR_RESENDE BIT(16)
|
|
|
|
|
#define SDCI_STAC_CLR_RESINDE BIT(17)
|
|
|
|
|
#define SDCI_STAC_CLR_RESCRCE BIT(18)
|
|
|
|
|
#define SDCI_STAC_CLR_WR_DATCRCE BIT(22)
|
|
|
|
|
#define SDCI_STAC_CLR_RD_DATCRCE BIT(23)
|
|
|
|
|
#define SDCI_STAC_CLR_RD_DATENDE0 BIT(24)
|
|
|
|
|
#define SDCI_STAC_CLR_RD_DATENDE1 BIT(25)
|
|
|
|
|
#define SDCI_STAC_CLR_RD_DATENDE2 BIT(26)
|
|
|
|
|
#define SDCI_STAC_CLR_RD_DATENDE3 BIT(27)
|
|
|
|
|
#define SDCI_STAC_CLR_RD_DATENDE4 BIT(28)
|
|
|
|
|
#define SDCI_STAC_CLR_RD_DATENDE5 BIT(29)
|
|
|
|
|
#define SDCI_STAC_CLR_RD_DATENDE6 BIT(30)
|
|
|
|
|
#define SDCI_STAC_CLR_RD_DATENDE7 BIT(31)
|
|
|
|
|
|
|
|
|
|
#define SDCI_DSTA_CMDRDY BIT(0)
|
|
|
|
|
#define SDCI_DSTA_CMDPRO BIT(1)
|
|
|
|
|
#define SDCI_DSTA_CMDEND BIT(2)
|
|
|
|
|
#define SDCI_DSTA_RESPRO BIT(3)
|
|
|
|
|
#define SDCI_DSTA_RESEND BIT(4)
|
|
|
|
|
#define SDCI_DSTA_DATPRO BIT(5)
|
|
|
|
|
#define SDCI_DSTA_DATEND BIT(6)
|
|
|
|
|
#define SDCI_DSTA_DAT_CRCEND BIT(7)
|
|
|
|
|
#define SDCI_DSTA_CRC_STAEND BIT(8)
|
|
|
|
|
#define SDCI_DSTA_DAT_BUSY BIT(9)
|
|
|
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#define SDCI_DSTA_SDCLK_HOLD BIT(12)
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#define SDCI_DSTA_DAT0_STATUS BIT(13)
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#define SDCI_DSTA_WP_DECT_INPUT BIT(14)
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#define SDCI_DSTA_RESTOUTE BIT(15)
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#define SDCI_DSTA_RESENDE BIT(16)
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#define SDCI_DSTA_RESINDE BIT(17)
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#define SDCI_DSTA_RESCRCE BIT(18)
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#define SDCI_DSTA_WR_CRC_STATUS_MASK BITRANGE(19, 21)
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#define SDCI_DSTA_WR_CRC_STATUS_OK BIT(20)
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#define SDCI_DSTA_WR_CRC_STATUS_TXERR (BIT(19) | BIT(21))
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#define SDCI_DSTA_WR_CRC_STATUS_CARDERR (BIT(19) | BIT(20) | BIT(21))
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#define SDCI_DSTA_WR_DATCRCE BIT(22)
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#define SDCI_DSTA_RD_DATCRCE BIT(23)
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#define SDCI_DSTA_RD_DATENDE0 BIT(24)
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#define SDCI_DSTA_RD_DATENDE1 BIT(25)
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#define SDCI_DSTA_RD_DATENDE2 BIT(26)
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#define SDCI_DSTA_RD_DATENDE3 BIT(27)
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#define SDCI_DSTA_RD_DATENDE4 BIT(28)
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#define SDCI_DSTA_RD_DATENDE5 BIT(29)
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#define SDCI_DSTA_RD_DATENDE6 BIT(30)
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#define SDCI_DSTA_RD_DATENDE7 BIT(31)
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#define SDCI_FSTA_RX_FIFO_EMPTY BIT(0)
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#define SDCI_FSTA_RX_FIFO_FULL BIT(1)
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#define SDCI_FSTA_TX_FIFO_EMPTY BIT(2)
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#define SDCI_FSTA_TX_FIFO_FULL BIT(3)
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#define SDCI_SDIO_CSR_SDIO_RW_EN BIT(0)
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#define SDCI_SDIO_CSR_SDIO_INT_EN BIT(1)
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#define SDCI_SDIO_CSR_SDIO_RW_REQ BIT(2)
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#define SDCI_SDIO_CSR_SDIO_RW_STOP BIT(3)
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#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MASK BIT(4)
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#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MORE 0
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#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_XACT BIT(4)
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#define SDCI_IRQ_DAT_DONE_INT BIT(0)
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#define SDCI_IRQ_IOCARD_IRQ_INT BIT(1)
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#define SDCI_IRQ_READ_WAIT_INT BIT(2)
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#define SDCI_IRQ_MASK_MASK_DAT_DONE_INT BIT(0)
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#define SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT BIT(1)
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#define SDCI_IRQ_MASK_MASK_READ_WAIT_INT BIT(2)
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/////CLICKWHEEL/////
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#define WHEEL00 (*((uint32_t volatile*)(0x3C200000)))
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#define WHEEL04 (*((uint32_t volatile*)(0x3C200004)))
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#define WHEEL08 (*((uint32_t volatile*)(0x3C200008)))
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#define WHEEL0C (*((uint32_t volatile*)(0x3C20000C)))
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#define WHEEL10 (*((uint32_t volatile*)(0x3C200010)))
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#define WHEELINT (*((uint32_t volatile*)(0x3C200014)))
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#define WHEELRX (*((uint32_t volatile*)(0x3C200018)))
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#define WHEELTX (*((uint32_t volatile*)(0x3C20001C)))
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/////I2S/////
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2015-09-25 23:35:15 +00:00
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#define I2SCLKGATE(i) ((i) == 2 ? CLOCKGATE_I2S2 : \
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(i) == 1 ? CLOCKGATE_I2S1 : \
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CLOCKGATE_I2S0)
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2011-11-06 22:44:25 +00:00
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#define I2SCLKCON (*((volatile uint32_t*)(0x3CA00000)))
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#define I2STXCON (*((volatile uint32_t*)(0x3CA00004)))
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#define I2STXCOM (*((volatile uint32_t*)(0x3CA00008)))
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#define I2STXDB0 (*((volatile uint32_t*)(0x3CA00010)))
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#define I2SRXCON (*((volatile uint32_t*)(0x3CA00030)))
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#define I2SRXCOM (*((volatile uint32_t*)(0x3CA00034)))
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#define I2SRXDB (*((volatile uint32_t*)(0x3CA00038)))
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#define I2SSTATUS (*((volatile uint32_t*)(0x3CA0003C)))
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2013-01-09 20:44:23 +00:00
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#define I2SCLKDIV (*((volatile uint32_t*)(0x3CA00040)))
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2011-11-06 22:44:25 +00:00
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2014-12-06 21:33:39 +00:00
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/////UART/////
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2016-05-12 04:47:38 +00:00
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/* s5l8702 UC870X HW: 1 UARTC, 4 ports */
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#define UARTC_BASE_ADDR 0x3CC00000
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#define UARTC_N_PORTS 4
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#define UARTC_PORT_OFFSET 0x4000
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2014-12-06 21:33:39 +00:00
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2011-11-06 22:44:25 +00:00
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/////CLOCK GATES/////
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2015-09-25 23:35:15 +00:00
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#define CLOCKGATE_SHA 0
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#define CLOCKGATE_LCD 1
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#define CLOCKGATE_USBOTG 2
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#define CLOCKGATE_SMx 3
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#define CLOCKGATE_SM1 4
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#define CLOCKGATE_ATA 5
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#define CLOCKGATE_SDCI 9
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#define CLOCKGATE_AES 10
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#define CLOCKGATE_DMAC0 25
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#define CLOCKGATE_DMAC1 26
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#define CLOCKGATE_ROM 30
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#define CLOCKGATE_RTC 32
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#define CLOCKGATE_CWHEEL 33
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#define CLOCKGATE_SPI0 34
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#define CLOCKGATE_USBPHY 35
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#define CLOCKGATE_I2C0 36
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#define CLOCKGATE_TIMER 37
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#define CLOCKGATE_I2C1 38
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#define CLOCKGATE_I2S0 39
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2016-05-12 04:47:38 +00:00
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#define CLOCKGATE_UARTC 41
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2015-09-25 23:35:15 +00:00
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#define CLOCKGATE_I2S1 42
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#define CLOCKGATE_SPI1 43
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#define CLOCKGATE_GPIO 44
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#define CLOCKGATE_CHIPID 46
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#define CLOCKGATE_I2S2 47
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#define CLOCKGATE_SPI2 48
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2011-11-06 22:44:25 +00:00
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/////INTERRUPTS/////
|
2015-09-25 23:35:15 +00:00
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#define IRQ_TIMER32 7
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#define IRQ_TIMER 8
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2016-05-25 21:54:24 +00:00
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#define IRQ_SPI(i) (9+(i)) /* TBC */
|
2015-09-25 23:35:15 +00:00
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#define IRQ_SPI0 9
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#define IRQ_SPI1 10
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#define IRQ_SPI2 11
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#define IRQ_LCD 14
|
2016-05-25 21:54:24 +00:00
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#define IRQ_DMAC(d) (16+(d))
|
2015-09-25 23:35:15 +00:00
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#define IRQ_DMAC0 16
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#define IRQ_DMAC1 17
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#define IRQ_USB_FUNC 19
|
2016-05-25 21:54:24 +00:00
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#define IRQ_I2C(i) (21+(i))
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#define IRQ_I2C0 21
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#define IRQ_I2C1 22
|
2015-09-25 23:35:15 +00:00
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#define IRQ_WHEEL 23
|
2016-05-25 21:54:24 +00:00
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|
#define IRQ_UART(i) (24+(i))
|
2015-09-25 23:35:15 +00:00
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|
#define IRQ_UART0 24
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#define IRQ_UART1 25
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#define IRQ_UART2 26
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#define IRQ_UART3 27
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#define IRQ_UART4 28 /* obsolete/not implemented on s5l8702 ??? */
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#define IRQ_ATA 29
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#define IRQ_SBOOT 36
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#define IRQ_AES 39
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#define IRQ_SHA 40
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|
#define IRQ_MMC 44
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|
#define IRQ_EXT0 0
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#define IRQ_EXT1 1
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#define IRQ_EXT2 2
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#define IRQ_EXT3 3
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#define IRQ_EXT4 31
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#define IRQ_EXT5 32
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|
#define IRQ_EXT6 33
|
2011-11-06 22:44:25 +00:00
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#endif
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